mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-28 21:03:54 -06:00
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
50d2b4d93f
commit
a8170e5e97
383 changed files with 2240 additions and 2240 deletions
162
exec.c
162
exec.c
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@ -398,13 +398,13 @@ static void phys_map_nodes_reset(void)
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}
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static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
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target_phys_addr_t *nb, uint16_t leaf,
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static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
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hwaddr *nb, uint16_t leaf,
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int level)
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{
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PhysPageEntry *p;
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int i;
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target_phys_addr_t step = (target_phys_addr_t)1 << (level * L2_BITS);
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hwaddr step = (hwaddr)1 << (level * L2_BITS);
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if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
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lp->ptr = phys_map_node_alloc();
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@ -434,7 +434,7 @@ static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
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}
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static void phys_page_set(AddressSpaceDispatch *d,
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target_phys_addr_t index, target_phys_addr_t nb,
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hwaddr index, hwaddr nb,
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uint16_t leaf)
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{
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/* Wildly overreserve - it doesn't matter much. */
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@ -443,7 +443,7 @@ static void phys_page_set(AddressSpaceDispatch *d,
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phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
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}
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MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, target_phys_addr_t index)
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MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
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{
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PhysPageEntry lp = d->phys_map;
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PhysPageEntry *p;
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@ -1473,7 +1473,7 @@ static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
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tb_invalidate_phys_page_range(pc, pc + 1, 0);
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}
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#else
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void tb_invalidate_phys_addr(target_phys_addr_t addr)
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void tb_invalidate_phys_addr(hwaddr addr)
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{
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ram_addr_t ram_addr;
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MemoryRegionSection *section;
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@ -1866,14 +1866,14 @@ int cpu_physical_memory_set_dirty_tracking(int enable)
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return ret;
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}
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target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
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hwaddr memory_region_section_get_iotlb(CPUArchState *env,
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MemoryRegionSection *section,
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target_ulong vaddr,
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target_phys_addr_t paddr,
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hwaddr paddr,
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int prot,
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target_ulong *address)
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{
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target_phys_addr_t iotlb;
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hwaddr iotlb;
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CPUWatchpoint *wp;
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if (memory_region_is_ram(section->mr)) {
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@ -2176,13 +2176,13 @@ int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
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#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
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typedef struct subpage_t {
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MemoryRegion iomem;
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target_phys_addr_t base;
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hwaddr base;
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uint16_t sub_section[TARGET_PAGE_SIZE];
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} subpage_t;
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static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
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uint16_t section);
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static subpage_t *subpage_init(target_phys_addr_t base);
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static subpage_t *subpage_init(hwaddr base);
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static void destroy_page_desc(uint16_t section_index)
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{
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MemoryRegionSection *section = &phys_sections[section_index];
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@ -2241,14 +2241,14 @@ static void phys_sections_clear(void)
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static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
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{
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subpage_t *subpage;
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target_phys_addr_t base = section->offset_within_address_space
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hwaddr base = section->offset_within_address_space
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& TARGET_PAGE_MASK;
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MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
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MemoryRegionSection subsection = {
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.offset_within_address_space = base,
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.size = TARGET_PAGE_SIZE,
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};
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target_phys_addr_t start, end;
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hwaddr start, end;
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assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
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@ -2268,9 +2268,9 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
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static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
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{
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target_phys_addr_t start_addr = section->offset_within_address_space;
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hwaddr start_addr = section->offset_within_address_space;
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ram_addr_t size = section->size;
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target_phys_addr_t addr;
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hwaddr addr;
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uint16_t section_index = phys_section_add(section);
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assert(size);
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@ -2836,7 +2836,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
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return ram_addr;
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}
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static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
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static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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#ifdef DEBUG_UNASSIGNED
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@ -2848,7 +2848,7 @@ static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
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static void unassigned_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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#ifdef DEBUG_UNASSIGNED
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@ -2865,13 +2865,13 @@ static const MemoryRegionOps unassigned_mem_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
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static uint64_t error_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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abort();
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}
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static void error_mem_write(void *opaque, target_phys_addr_t addr,
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static void error_mem_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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abort();
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@ -2889,7 +2889,7 @@ static const MemoryRegionOps rom_mem_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
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static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
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uint64_t val, unsigned size)
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{
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int dirty_flags;
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@ -2976,7 +2976,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
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/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
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so these check for a hit then pass through to the normal out-of-line
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phys routines. */
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static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
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static uint64_t watch_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
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@ -2988,7 +2988,7 @@ static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
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}
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}
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static void watch_mem_write(void *opaque, target_phys_addr_t addr,
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static void watch_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
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@ -3012,7 +3012,7 @@ static const MemoryRegionOps watch_mem_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
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static uint64_t subpage_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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subpage_t *mmio = opaque;
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@ -3030,7 +3030,7 @@ static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
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return io_mem_read(section->mr, addr, len);
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}
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static void subpage_write(void *opaque, target_phys_addr_t addr,
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static void subpage_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned len)
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{
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subpage_t *mmio = opaque;
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@ -3055,7 +3055,7 @@ static const MemoryRegionOps subpage_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
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static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ram_addr_t raddr = addr;
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@ -3068,7 +3068,7 @@ static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
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}
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}
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static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
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static void subpage_ram_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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ram_addr_t raddr = addr;
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@ -3112,7 +3112,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
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return 0;
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}
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static subpage_t *subpage_init(target_phys_addr_t base)
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static subpage_t *subpage_init(hwaddr base)
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{
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subpage_t *mmio;
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@ -3143,7 +3143,7 @@ static uint16_t dummy_section(MemoryRegion *mr)
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return phys_section_add(§ion);
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}
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MemoryRegion *iotlb_to_region(target_phys_addr_t index)
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MemoryRegion *iotlb_to_region(hwaddr index)
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{
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return phys_sections[index & ~TARGET_PAGE_MASK].mr;
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}
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@ -3333,8 +3333,8 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
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#else
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static void invalidate_and_set_dirty(target_phys_addr_t addr,
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target_phys_addr_t length)
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static void invalidate_and_set_dirty(hwaddr addr,
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hwaddr length)
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{
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if (!cpu_physical_memory_is_dirty(addr)) {
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/* invalidate code */
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@ -3345,14 +3345,14 @@ static void invalidate_and_set_dirty(target_phys_addr_t addr,
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xen_modified_memory(addr, length);
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}
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void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
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void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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int len, bool is_write)
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{
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AddressSpaceDispatch *d = as->dispatch;
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int l;
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uint8_t *ptr;
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uint32_t val;
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target_phys_addr_t page;
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hwaddr page;
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MemoryRegionSection *section;
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while (len > 0) {
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@ -3364,7 +3364,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
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if (is_write) {
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if (!memory_region_is_ram(section->mr)) {
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target_phys_addr_t addr1;
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hwaddr addr1;
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addr1 = memory_region_section_addr(section, addr);
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/* XXX: could force cpu_single_env to NULL to avoid
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potential bugs */
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@ -3397,7 +3397,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
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} else {
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if (!(memory_region_is_ram(section->mr) ||
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memory_region_is_romd(section->mr))) {
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target_phys_addr_t addr1;
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hwaddr addr1;
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/* I/O case */
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addr1 = memory_region_section_addr(section, addr);
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if (l >= 4 && ((addr1 & 3) == 0)) {
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@ -3431,7 +3431,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
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}
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}
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void address_space_write(AddressSpace *as, target_phys_addr_t addr,
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void address_space_write(AddressSpace *as, hwaddr addr,
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const uint8_t *buf, int len)
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{
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address_space_rw(as, addr, (uint8_t *)buf, len, true);
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@ -3444,26 +3444,26 @@ void address_space_write(AddressSpace *as, target_phys_addr_t addr,
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* @addr: address within that address space
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* @buf: buffer with the data transferred
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*/
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void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len)
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void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
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{
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address_space_rw(as, addr, buf, len, false);
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}
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
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int len, int is_write)
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{
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return address_space_rw(&address_space_memory, addr, buf, len, is_write);
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}
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/* used for ROM loading : can write in RAM and ROM */
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void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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void cpu_physical_memory_write_rom(hwaddr addr,
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const uint8_t *buf, int len)
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{
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AddressSpaceDispatch *d = address_space_memory.dispatch;
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int l;
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uint8_t *ptr;
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target_phys_addr_t page;
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hwaddr page;
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MemoryRegionSection *section;
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while (len > 0) {
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@ -3494,8 +3494,8 @@ void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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typedef struct {
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void *buffer;
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target_phys_addr_t addr;
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target_phys_addr_t len;
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hwaddr addr;
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hwaddr len;
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} BounceBuffer;
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static BounceBuffer bounce;
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@ -3546,15 +3546,15 @@ static void cpu_notify_map_clients(void)
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* likely to succeed.
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*/
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void *address_space_map(AddressSpace *as,
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target_phys_addr_t addr,
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target_phys_addr_t *plen,
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hwaddr addr,
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hwaddr *plen,
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bool is_write)
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{
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AddressSpaceDispatch *d = as->dispatch;
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target_phys_addr_t len = *plen;
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target_phys_addr_t todo = 0;
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hwaddr len = *plen;
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hwaddr todo = 0;
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int l;
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target_phys_addr_t page;
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hwaddr page;
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MemoryRegionSection *section;
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ram_addr_t raddr = RAM_ADDR_MAX;
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ram_addr_t rlen;
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@ -3600,8 +3600,8 @@ void *address_space_map(AddressSpace *as,
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* Will also mark the memory as dirty if is_write == 1. access_len gives
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* the amount of memory that was actually read or written by the caller.
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*/
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void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
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int is_write, target_phys_addr_t access_len)
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void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
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int is_write, hwaddr access_len)
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{
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if (buffer != bounce.buffer) {
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if (is_write) {
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@ -3629,21 +3629,21 @@ void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
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cpu_notify_map_clients();
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}
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void *cpu_physical_memory_map(target_phys_addr_t addr,
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target_phys_addr_t *plen,
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void *cpu_physical_memory_map(hwaddr addr,
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hwaddr *plen,
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int is_write)
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{
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return address_space_map(&address_space_memory, addr, plen, is_write);
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}
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void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
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int is_write, target_phys_addr_t access_len)
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void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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int is_write, hwaddr access_len)
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{
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return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
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}
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/* warning: addr must be aligned */
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static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
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static inline uint32_t ldl_phys_internal(hwaddr addr,
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enum device_endian endian)
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{
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uint8_t *ptr;
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|
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@ -3686,23 +3686,23 @@ static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
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return val;
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}
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uint32_t ldl_phys(target_phys_addr_t addr)
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uint32_t ldl_phys(hwaddr addr)
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{
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return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
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}
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uint32_t ldl_le_phys(target_phys_addr_t addr)
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uint32_t ldl_le_phys(hwaddr addr)
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{
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return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
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}
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uint32_t ldl_be_phys(target_phys_addr_t addr)
|
||||
uint32_t ldl_be_phys(hwaddr addr)
|
||||
{
|
||||
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
/* warning: addr must be aligned */
|
||||
static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
|
||||
static inline uint64_t ldq_phys_internal(hwaddr addr,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
|
|
@ -3745,23 +3745,23 @@ static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
|
|||
return val;
|
||||
}
|
||||
|
||||
uint64_t ldq_phys(target_phys_addr_t addr)
|
||||
uint64_t ldq_phys(hwaddr addr)
|
||||
{
|
||||
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
uint64_t ldq_le_phys(target_phys_addr_t addr)
|
||||
uint64_t ldq_le_phys(hwaddr addr)
|
||||
{
|
||||
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
uint64_t ldq_be_phys(target_phys_addr_t addr)
|
||||
uint64_t ldq_be_phys(hwaddr addr)
|
||||
{
|
||||
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
/* XXX: optimize */
|
||||
uint32_t ldub_phys(target_phys_addr_t addr)
|
||||
uint32_t ldub_phys(hwaddr addr)
|
||||
{
|
||||
uint8_t val;
|
||||
cpu_physical_memory_read(addr, &val, 1);
|
||||
|
|
@ -3769,7 +3769,7 @@ uint32_t ldub_phys(target_phys_addr_t addr)
|
|||
}
|
||||
|
||||
/* warning: addr must be aligned */
|
||||
static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
|
||||
static inline uint32_t lduw_phys_internal(hwaddr addr,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
|
|
@ -3812,17 +3812,17 @@ static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
|
|||
return val;
|
||||
}
|
||||
|
||||
uint32_t lduw_phys(target_phys_addr_t addr)
|
||||
uint32_t lduw_phys(hwaddr addr)
|
||||
{
|
||||
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
uint32_t lduw_le_phys(target_phys_addr_t addr)
|
||||
uint32_t lduw_le_phys(hwaddr addr)
|
||||
{
|
||||
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
uint32_t lduw_be_phys(target_phys_addr_t addr)
|
||||
uint32_t lduw_be_phys(hwaddr addr)
|
||||
{
|
||||
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
|
@ -3830,7 +3830,7 @@ uint32_t lduw_be_phys(target_phys_addr_t addr)
|
|||
/* warning: addr must be aligned. The ram page is not masked as dirty
|
||||
and the code inside is not invalidated. It is useful if the dirty
|
||||
bits are used to track modified PTEs */
|
||||
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
|
||||
void stl_phys_notdirty(hwaddr addr, uint32_t val)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
MemoryRegionSection *section;
|
||||
|
|
@ -3862,7 +3862,7 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
|
|||
}
|
||||
}
|
||||
|
||||
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
|
||||
void stq_phys_notdirty(hwaddr addr, uint64_t val)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
MemoryRegionSection *section;
|
||||
|
|
@ -3890,7 +3890,7 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
|
|||
}
|
||||
|
||||
/* warning: addr must be aligned */
|
||||
static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
|
||||
static inline void stl_phys_internal(hwaddr addr, uint32_t val,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
|
|
@ -3934,30 +3934,30 @@ static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
|
|||
}
|
||||
}
|
||||
|
||||
void stl_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stl_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
void stl_le_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stl_le_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
void stl_be_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stl_be_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
/* XXX: optimize */
|
||||
void stb_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stb_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
uint8_t v = val;
|
||||
cpu_physical_memory_write(addr, &v, 1);
|
||||
}
|
||||
|
||||
/* warning: addr must be aligned */
|
||||
static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
|
||||
static inline void stw_phys_internal(hwaddr addr, uint32_t val,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
|
|
@ -4001,35 +4001,35 @@ static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
|
|||
}
|
||||
}
|
||||
|
||||
void stw_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stw_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
void stw_le_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stw_le_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
void stw_be_phys(target_phys_addr_t addr, uint32_t val)
|
||||
void stw_be_phys(hwaddr addr, uint32_t val)
|
||||
{
|
||||
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
/* XXX: optimize */
|
||||
void stq_phys(target_phys_addr_t addr, uint64_t val)
|
||||
void stq_phys(hwaddr addr, uint64_t val)
|
||||
{
|
||||
val = tswap64(val);
|
||||
cpu_physical_memory_write(addr, &val, 8);
|
||||
}
|
||||
|
||||
void stq_le_phys(target_phys_addr_t addr, uint64_t val)
|
||||
void stq_le_phys(hwaddr addr, uint64_t val)
|
||||
{
|
||||
val = cpu_to_le64(val);
|
||||
cpu_physical_memory_write(addr, &val, 8);
|
||||
}
|
||||
|
||||
void stq_be_phys(target_phys_addr_t addr, uint64_t val)
|
||||
void stq_be_phys(hwaddr addr, uint64_t val)
|
||||
{
|
||||
val = cpu_to_be64(val);
|
||||
cpu_physical_memory_write(addr, &val, 8);
|
||||
|
|
@ -4040,7 +4040,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
|
|||
uint8_t *buf, int len, int is_write)
|
||||
{
|
||||
int l;
|
||||
target_phys_addr_t phys_addr;
|
||||
hwaddr phys_addr;
|
||||
target_ulong page;
|
||||
|
||||
while (len > 0) {
|
||||
|
|
@ -4195,7 +4195,7 @@ bool virtio_is_big_endian(void)
|
|||
#endif
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr)
|
||||
bool cpu_physical_memory_is_io(hwaddr phys_addr)
|
||||
{
|
||||
MemoryRegionSection *section;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue