mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 16:53:55 -06:00
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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# kh+aFEdKajPp56UseJiKBQ==
# =5Shq
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
target/arm: Enable SCTLR_EL1.TIDCP for user-only
target/arm: Implement FEAT_TIDCP1
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement cortex-a710
target/arm: Implement RMR_ELx
arm64: Restore trapless ptimer access
target/arm: Do not use gen_mte_checkN in trans_STGP
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc: Introduce the Xilinx CFI interface
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_Pauth2
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
a7e8e30e7c
40 changed files with 3184 additions and 157 deletions
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@ -417,12 +417,22 @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type)
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{
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assert_has_feature_enabled(qts, cpu_type, "pauth");
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assert_has_feature_disabled(qts, cpu_type, "pauth-impdef");
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assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3");
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assert_set_feature(qts, cpu_type, "pauth", false);
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assert_set_feature(qts, cpu_type, "pauth", true);
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assert_set_feature(qts, cpu_type, "pauth-impdef", true);
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assert_set_feature(qts, cpu_type, "pauth-impdef", false);
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assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth",
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assert_set_feature(qts, cpu_type, "pauth-qarma3", true);
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assert_set_feature(qts, cpu_type, "pauth-qarma3", false);
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assert_error(qts, cpu_type,
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"cannot enable pauth-impdef or pauth-qarma3 without pauth",
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"{ 'pauth': false, 'pauth-impdef': true }");
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assert_error(qts, cpu_type,
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"cannot enable pauth-impdef or pauth-qarma3 without pauth",
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"{ 'pauth': false, 'pauth-qarma3': true }");
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assert_error(qts, cpu_type,
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"cannot enable both pauth-impdef and pauth-qarma3",
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"{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true }");
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}
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static void test_query_cpu_model_expansion(const void *data)
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@ -42,7 +42,11 @@ endif
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ifneq ($(CROSS_CC_HAS_ARMV8_3),)
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AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
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pauth-%: CFLAGS += -march=armv8.3-a
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run-pauth-%: QEMU_OPTS += -cpu max
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run-pauth-1: QEMU_OPTS += -cpu max
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run-pauth-2: QEMU_OPTS += -cpu max
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# Choose a cpu with FEAT_Pauth but without FEAT_FPAC for pauth-[45].
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run-pauth-4: QEMU_OPTS += -cpu neoverse-v1
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run-pauth-5: QEMU_OPTS += -cpu neoverse-v1
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endif
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# BTI Tests
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@ -1,5 +1,22 @@
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#include <stdint.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <assert.h>
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#include "pauth.h"
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static void sigill(int sig, siginfo_t *info, void *vuc)
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{
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ucontext_t *uc = vuc;
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uint64_t test;
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/* There is only one insn below that is allowed to fault. */
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asm volatile("adr %0, auth2_insn" : "=r"(test));
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assert(test == uc->uc_mcontext.pc);
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exit(0);
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}
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static int pac_feature;
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void do_test(uint64_t value)
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{
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@ -27,31 +44,52 @@ void do_test(uint64_t value)
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* An invalid salt usually fails authorization, but again there
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* is a chance of choosing another salt that works.
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* Iterate until we find another salt which does fail.
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*
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* With FEAT_FPAC, this will SIGILL instead of producing a result.
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*/
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for (salt2 = salt1 + 1; ; salt2++) {
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asm volatile("autda %0, %2" : "=r"(decode) : "0"(encode), "r"(salt2));
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asm volatile("auth2_insn: autda %0, %2"
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: "=r"(decode) : "0"(encode), "r"(salt2));
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if (decode != value) {
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break;
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}
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}
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assert(pac_feature < 4); /* No FEAT_FPAC */
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/* The VA bits, bit 55, and the TBI bits, should be unchanged. */
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assert(((decode ^ value) & 0xff80ffffffffffffull) == 0);
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/*
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* Bits [54:53] are an error indicator based on the key used;
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* the DA key above is keynumber 0, so error == 0b01. Otherwise
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* bit 55 of the original is sign-extended into the rest of the auth.
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* Without FEAT_Pauth2, bits [54:53] are an error indicator based on
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* the key used; the DA key above is keynumber 0, so error == 0b01.
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* Otherwise, bit 55 of the original is sign-extended into the rest
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* of the auth.
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*/
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if ((value >> 55) & 1) {
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assert(((decode >> 48) & 0xff) == 0b10111111);
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} else {
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assert(((decode >> 48) & 0xff) == 0b00100000);
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if (pac_feature < 3) {
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if ((value >> 55) & 1) {
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assert(((decode >> 48) & 0xff) == 0b10111111);
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} else {
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assert(((decode >> 48) & 0xff) == 0b00100000);
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}
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}
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}
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int main()
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{
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static const struct sigaction sa = {
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.sa_sigaction = sigill,
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.sa_flags = SA_SIGINFO
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};
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pac_feature = get_pac_feature();
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assert(pac_feature != 0);
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if (pac_feature >= 4) {
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/* FEAT_FPAC */
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sigaction(SIGILL, &sa, NULL);
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}
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do_test(0);
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do_test(0xda004acedeadbeefull);
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return 0;
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@ -2,14 +2,24 @@
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#include <assert.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "pauth.h"
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#define TESTS 1000
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int main()
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{
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char base[TESTS];
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int i, count = 0;
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float perc;
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void *base = malloc(TESTS);
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int pac_feature = get_pac_feature();
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/*
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* Exit if no PAuth or FEAT_FPAC, which will SIGILL on AUTIA failure
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* rather than return an error for us to check below.
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*/
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if (pac_feature == 0 || pac_feature >= 4) {
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return 0;
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}
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for (i = 0; i < TESTS; i++) {
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uintptr_t in, x, y;
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@ -17,7 +27,7 @@ int main()
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in = i + (uintptr_t) base;
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asm("mov %0, %[in]\n\t"
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"pacia %0, sp\n\t" /* sigill if pauth not supported */
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"pacia %0, sp\n\t"
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"eor %0, %0, #4\n\t" /* corrupt single bit */
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"mov %1, %0\n\t"
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"autia %1, sp\n\t" /* validate corrupted pointer */
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@ -36,10 +46,10 @@ int main()
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if (x != y) {
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count++;
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}
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}
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perc = (float) count / (float) TESTS;
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printf("Checks Passed: %0.2f%%", perc * 100.0);
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printf("Checks Passed: %0.2f%%\n", perc * 100.0);
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assert(perc > 0.95);
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return 0;
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}
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@ -1,4 +1,5 @@
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#include <assert.h>
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#include "pauth.h"
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static int x;
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@ -6,6 +7,15 @@ int main()
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{
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int *p0 = &x, *p1, *p2, *p3;
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unsigned long salt = 0;
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int pac_feature = get_pac_feature();
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/*
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* Exit if no PAuth or FEAT_FPAC, which will SIGILL on AUTDA failure
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* rather than return an error for us to check below.
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*/
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if (pac_feature == 0 || pac_feature >= 4) {
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return 0;
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}
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/*
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* With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
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23
tests/tcg/aarch64/pauth.h
Normal file
23
tests/tcg/aarch64/pauth.h
Normal file
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@ -0,0 +1,23 @@
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/*
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* Helper for pauth test case
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*
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* Copyright (c) 2023 Linaro Ltd
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <assert.h>
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#include <sys/auxv.h>
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static int get_pac_feature(void)
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{
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unsigned long isar1, isar2;
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assert(getauxval(AT_HWCAP) & HWCAP_CPUID);
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asm("mrs %0, id_aa64isar1_el1" : "=r"(isar1));
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asm("mrs %0, S3_0_C0_C6_2" : "=r"(isar2)); /* id_aa64isar2_el1 */
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return ((isar1 >> 4) & 0xf) /* APA */
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| ((isar1 >> 8) & 0xf) /* API */
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| ((isar2 >> 12) & 0xf); /* APA3 */
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}
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