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https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
target/arm: Enable SCTLR_EL1.TIDCP for user-only
target/arm: Implement FEAT_TIDCP1
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement cortex-a710
target/arm: Implement RMR_ELx
arm64: Restore trapless ptimer access
target/arm: Do not use gen_mte_checkN in trans_STGP
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc: Introduce the Xilinx CFI interface
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_Pauth2
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
a7e8e30e7c
40 changed files with 3184 additions and 157 deletions
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@ -1033,6 +1033,7 @@ struct ArchCPU {
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uint32_t dbgdevid1;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64isar2;
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uint64_t id_aa64pfr0;
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uint64_t id_aa64pfr1;
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uint64_t id_aa64mmfr0;
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@ -1071,6 +1072,7 @@ struct ArchCPU {
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*/
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bool prop_pauth;
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bool prop_pauth_impdef;
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bool prop_pauth_qarma3;
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bool prop_lpa2;
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/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
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@ -3795,28 +3797,59 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
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}
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/*
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* These are the values from APA/API/APA3.
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* In general these must be compared '>=', per the normal Arm ARM
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* treatment of fields in ID registers.
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*/
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typedef enum {
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PauthFeat_None = 0,
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PauthFeat_1 = 1,
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PauthFeat_EPAC = 2,
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PauthFeat_2 = 3,
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PauthFeat_FPAC = 4,
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PauthFeat_FPACCOMBINED = 5,
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} ARMPauthFeature;
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static inline ARMPauthFeature
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isar_feature_pauth_feature(const ARMISARegisters *id)
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{
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/*
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* Architecturally, only one of {APA,API,APA3} may be active (non-zero)
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* and the other two must be zero. Thus we may avoid conditionals.
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*/
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return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
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FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
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FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
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}
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static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
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{
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/*
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* Return true if any form of pauth is enabled, as this
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* predicate controls migration of the 128-bit keys.
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*/
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return (id->id_aa64isar1 &
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(FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
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return isar_feature_pauth_feature(id) != PauthFeat_None;
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}
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static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
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{
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/*
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* Return true if pauth is enabled with the architected QARMA algorithm.
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* QEMU will always set APA+GPA to the same value.
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* Return true if pauth is enabled with the architected QARMA5 algorithm.
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* QEMU will always enable or disable both APA and GPA.
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*/
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
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}
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static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
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{
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/*
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* Return true if pauth is enabled with the architected QARMA3 algorithm.
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* QEMU will always enable or disable both APA3 and GPA3.
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*/
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
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}
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static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
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@ -3939,6 +3972,11 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
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}
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static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
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}
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static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
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