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hw/mips/gt64xxx_pci: Move it to hw/pci-host/
The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221209151533.69516-8-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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8 changed files with 15 additions and 15 deletions
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@ -60,9 +60,3 @@ config MIPS_BOSTON
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config FW_CFG_MIPS
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bool
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config GT64120
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bool
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select PCI
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select EMPTY_SLOT
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select I8259
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File diff suppressed because it is too large
Load diff
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@ -3,7 +3,6 @@ mips_ss.add(files('bootloader.c', 'mips_int.c'))
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mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
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mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
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mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c'))
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softmmu_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64xxx_pci.c'))
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mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'))
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if 'CONFIG_TCG' in config_all
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@ -1,10 +1,3 @@
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# gt64xxx_pci.c
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gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
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gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
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gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
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gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
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gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
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# malta.c
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malta_fpga_leds(const char *text) "LEDs %s"
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malta_fpga_display(const char *text) "ASCII '%s'"
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