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Great rework and cleanups to ease PowerPC implementations definitions.

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* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-09-26 23:54:22 +00:00
parent 08fa4bab83
commit a750fc0b91
11 changed files with 4346 additions and 3189 deletions
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7
hw/ppc.c
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@ -376,11 +376,11 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the external IRQ state to %d\n",
fprintf(logfile, "%s: set the debug pin state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, EXCP_40x_DEBUG, level);
ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
@ -904,6 +904,9 @@ struct ppc_dcrn_t {
void *opaque;
};
/* XXX: on 460, DCR addresses are 32 bits wide,
* using DCRIPR to get the 22 upper bits of the DCR address
*/
#define DCRN_NB 1024
struct ppc_dcr_t {
ppc_dcrn_t dcrn[DCRN_NB];