mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 09:13:55 -06:00
PPC: e500: Fix MMUCSR0 emulation
A "mtspr SPRMMUCSR0, reg" always flushed TLB0, because it passed the SPR number 0x3f4 to the flush routine. But we want to flush either TLB0 or TBL1 depending on the GPR value. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> [agraf: change subject line, fix TCGv size mismatch] Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
parent
1b8eceee28
commit
a721d390b3
3 changed files with 3 additions and 5 deletions
|
@ -539,7 +539,7 @@ DEF_HELPER_2(booke206_tlbivax, void, env, tl)
|
|||
DEF_HELPER_2(booke206_tlbilx0, void, env, tl)
|
||||
DEF_HELPER_2(booke206_tlbilx1, void, env, tl)
|
||||
DEF_HELPER_2(booke206_tlbilx3, void, env, tl)
|
||||
DEF_HELPER_2(booke206_tlbflush, void, env, i32)
|
||||
DEF_HELPER_2(booke206_tlbflush, void, env, tl)
|
||||
DEF_HELPER_3(booke_setpid, void, env, i32, tl)
|
||||
DEF_HELPER_2(6xx_tlbd, void, env, tl)
|
||||
DEF_HELPER_2(6xx_tlbi, void, env, tl)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue