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hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

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Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-08-30 15:34:36 +10:00
parent 0f0b70eeec
commit a714b8aa02
2 changed files with 52 additions and 22 deletions
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2
include/hw/intc/sifive_clint.h
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@ -40,6 +40,8 @@ typedef struct SiFiveCLINTState {
uint32_t time_base;
uint32_t aperture_size;
uint32_t timebase_freq;
qemu_irq *timer_irqs;
qemu_irq *soft_irqs;
} SiFiveCLINTState;
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,