motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-15 22:21:57 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/hppa: Remove get_temp_tl

Browse source 
Replace with tcg_temp_new_tl without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 21:05:03 -07:00
parent e12c63090b
commit a6779861fd
1 changed files with 3 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

28
target/hppa/translate.c
View file

@ -254,9 +254,6 @@ typedef struct DisasContext {
target_ureg iaoq_n; target_ureg iaoq_n;
TCGv_reg iaoq_n_var; TCGv_reg iaoq_n_var;
int ntempl;
TCGv_tl templ[4];
DisasCond null_cond; DisasCond null_cond;
TCGLabel *null_lab; TCGLabel *null_lab;
@ -491,15 +488,6 @@ static void cond_free(DisasCond *cond)
} }
} }
#ifndef CONFIG_USER_ONLY
static TCGv_tl get_temp_tl(DisasContext *ctx)
{
unsigned i = ctx->ntempl++;
g_assert(i < ARRAY_SIZE(ctx->templ));
return ctx->templ[i] = tcg_temp_new_tl();
}
#endif
static TCGv_reg load_const(DisasContext *ctx, target_sreg v) static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
{ {
TCGv_reg t = tcg_temp_new(); TCGv_reg t = tcg_temp_new();
@ -1374,7 +1362,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
if (sp < 0) { if (sp < 0) {
sp = ~sp; sp = ~sp;
} }
spc = get_temp_tl(ctx); spc = tcg_temp_new_tl();
load_spr(ctx, spc, sp); load_spr(ctx, spc, sp);
return spc; return spc;
} }
@ -1384,7 +1372,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
ptr = tcg_temp_new_ptr(); ptr = tcg_temp_new_ptr();
tmp = tcg_temp_new(); tmp = tcg_temp_new();
spc = get_temp_tl(ctx); spc = tcg_temp_new_tl();
tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_andi_reg(tmp, tmp, 030);
@ -1420,7 +1408,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
*pgva = (modify <= 0 ? ofs : base); *pgva = (modify <= 0 ? ofs : base);
#else #else
TCGv_tl addr = get_temp_tl(ctx); TCGv_tl addr = tcg_temp_new_tl();
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
if (ctx->tb_flags & PSW_W) { if (ctx->tb_flags & PSW_W) {
tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull);
@ -4081,9 +4069,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
/* Bound the number of instructions by those left on the page. */ /* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound); ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntempl = 0;
memset(ctx->templ, 0, sizeof(ctx->templ));
} }
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
@ -4112,7 +4097,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUHPPAState *env = cpu_env(cs); CPUHPPAState *env = cpu_env(cs);
DisasJumpType ret; DisasJumpType ret;
int i, n;
/* Execute one insn. */ /* Execute one insn. */
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
@ -4151,12 +4135,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
} }
} }
/* Forget any temporaries allocated. */
for (i = 0, n = ctx->ntempl; i < n; ++i) {
ctx->templ[i] = NULL;
}
ctx->ntempl = 0;
/* Advance the insn queue. Note that this check also detects /* Advance the insn queue. Note that this check also detects
a priority change within the instruction queue. */ a priority change within the instruction queue. */
if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) {