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PL031 qdev conversion

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Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook 2009-05-14 22:35:07 +01:00
parent a558046625
commit a63bdb3102
5 changed files with 16 additions and 14 deletions
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2
hw/integratorcp.c
View file

@ -481,7 +481,7 @@ static void integratorcp_init(ram_addr_t ram_size,
cpu_pic[ARM_PIC_CPU_FIQ]); cpu_pic[ARM_PIC_CPU_FIQ]);
icp_pic_init(0xca000000, pic[26], NULL); icp_pic_init(0xca000000, pic[26], NULL);
icp_pit_init(0x13000000, pic, 5); icp_pit_init(0x13000000, pic, 5);
pl031_init(0x15000000, pic[8]); sysbus_create_simple("pl031", 0x15000000, pic[8]);
sysbus_create_simple("pl011", 0x16000000, pic[1]); sysbus_create_simple("pl011", 0x16000000, pic[1]);
sysbus_create_simple("pl011", 0x17000000, pic[2]); sysbus_create_simple("pl011", 0x17000000, pic[2]);
icp_control_init(0xcb000000); icp_control_init(0xcb000000);

21
hw/pl031.c
View file

@ -9,8 +9,7 @@
* *
*/ */
#include "hw.h" #include "sysbus.h"
#include "primecell.h"
#include "qemu-timer.h" #include "qemu-timer.h"
//#define DEBUG_PL031 //#define DEBUG_PL031
@ -32,6 +31,7 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
#define RTC_ICR 0x1c /* Interrupt clear register */ #define RTC_ICR 0x1c /* Interrupt clear register */
typedef struct { typedef struct {
SysBusDevice busdev;
QEMUTimer *timer; QEMUTimer *timer;
qemu_irq irq; qemu_irq irq;
@ -183,25 +183,30 @@ static CPUReadMemoryFunc * pl031_readfn[] = {
pl031_read pl031_read
}; };
void pl031_init(uint32_t base, qemu_irq irq) static void pl031_init(SysBusDevice *dev)
{ {
int iomemtype; int iomemtype;
pl031_state *s; pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm; struct tm tm;
s = qemu_mallocz(sizeof(pl031_state));
iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s); iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
if (iomemtype == -1) { if (iomemtype == -1) {
hw_error("pl031_init: Can't register I/O memory\n"); hw_error("pl031_init: Can't register I/O memory\n");
} }
cpu_register_physical_memory(base, 0x00001000, iomemtype); sysbus_init_mmio(dev, 0x1000, iomemtype);
s->irq = irq; sysbus_init_irq(dev, &s->irq);
/* ??? We assume vm_clock is zero at this point. */ /* ??? We assume vm_clock is zero at this point. */
qemu_get_timedate(&tm, 0); qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm); s->tick_offset = mktimegm(&tm);
s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
} }
static void pl031_register_devices(void)
{
sysbus_register_dev("pl031", sizeof(pl031_state), pl031_init);
}
device_init(pl031_register_devices)

3
hw/primecell.h
View file

@ -5,9 +5,6 @@
/* Also includes some devices that are currently only used by the /* Also includes some devices that are currently only used by the
ARM boards. */ ARM boards. */
/* pl031.c */
void pl031_init(uint32_t base, qemu_irq irq);
/* pl022.c */ /* pl022.c */
typedef int (*ssi_xfer_cb)(void *, int); typedef int (*ssi_xfer_cb)(void *, int);
void pl022_init(uint32_t base, qemu_irq irq, ssi_xfer_cb xfer_cb, void pl022_init(uint32_t base, qemu_irq irq, ssi_xfer_cb xfer_cb,

2
hw/realview.c
View file

@ -104,7 +104,7 @@ static void realview_init(ram_addr_t ram_size,
} }
pl181_init(0x10005000, drives_table[index].bdrv, pic[17], pic[18]); pl181_init(0x10005000, drives_table[index].bdrv, pic[17], pic[18]);
pl031_init(0x10017000, pic[10]); sysbus_create_simple("pl031", 0x10017000, pic[10]);
pci_bus = pci_vpb_init(pic, 48, 1); pci_bus = pci_vpb_init(pic, 48, 1);
if (usb_enabled) { if (usb_enabled) {

2
hw/versatilepb.c
View file

@ -237,7 +237,7 @@ static void versatile_init(ram_addr_t ram_size,
#endif #endif
/* Add PL031 Real Time Clock. */ /* Add PL031 Real Time Clock. */
pl031_init(0x101e8000,pic[10]); sysbus_create_simple("pl031", 0x101e8000, pic[10]);
/* Memory map for Versatile/PB: */ /* Memory map for Versatile/PB: */
/* 0x10000000 System registers. */ /* 0x10000000 System registers. */