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target/arm: Define an aa32_pmu_8_1 isar feature test function

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Instead of open-coding a check on the ID_DFR0 PerfMon ID register
field, create a standardly-named isar_feature for "does AArch32 have
a v8.1 PMUv3" and use it.

This entails moving the id_dfr0 field into the ARMISARegisters struct.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-02-14 17:51:03 +00:00
parent d52c061e54
commit a617953855
5 changed files with 28 additions and 22 deletions
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9
target/arm/cpu.h
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@ -865,6 +865,7 @@ struct ARMCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
uint32_t id_dfr0;
uint64_t id_aa64isar0;
uint64_t id_aa64isar1;
uint64_t id_aa64pfr0;
@ -880,7 +881,6 @@ struct ARMCPU {
uint32_t reset_sctlr;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
uint64_t pmceid0;
uint64_t pmceid1;
uint32_t id_afr0;
@ -3500,6 +3500,13 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
}
static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
}
/*
* 64-bit feature tests via id registers.
*/