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trans_rvv.c.inc: remove 'is_store' bool from load/store fns

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After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in some load/store functions that were changed. Remove it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240306171932.549549-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-03-06 14:19:25 -03:00 • committed by Alistair Francis
parent 944b6dfd3d
commit a506c4289d
1 changed files with 29 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

58
target/riscv/insn_trans/trans_rvv.c.inc
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@ -796,7 +796,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn, uint32_t data, gen_helper_ldst_stride *fn,
DisasContext *s, bool is_store) DisasContext *s)
{ {
TCGv_ptr dest, mask; TCGv_ptr dest, mask;
TCGv base, stride; TCGv base, stride;
@ -843,7 +843,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
} }
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@ -877,7 +877,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
return false; return false;
} }
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
} }
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@ -900,7 +900,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn, uint32_t data, gen_helper_ldst_index *fn,
DisasContext *s, bool is_store) DisasContext *s)
{ {
TCGv_ptr dest, mask, index; TCGv_ptr dest, mask, index;
TCGv base; TCGv base;
@ -967,7 +967,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
} }
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@ -1019,7 +1019,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
} }
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@ -1098,7 +1098,7 @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn, uint32_t width, gen_helper_ldst_whole *fn,
DisasContext *s, bool is_store) DisasContext *s)
{ {
uint32_t evl = s->cfg_ptr->vlenb * nf / width; uint32_t evl = s->cfg_ptr->vlenb * nf / width;
TCGLabel *over = gen_new_label(); TCGLabel *over = gen_new_label();
@ -1129,42 +1129,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
* load and store whole register instructions ignore vtype and vl setting. * load and store whole register instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 7.9) * Thus, we don't need to check vill bit. (Section 7.9)
*/ */
#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \ #define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \ { \
if (require_rvv(s) && \ if (require_rvv(s) && \
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \ return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
gen_helper_##NAME, s, IS_STORE); \ gen_helper_##NAME, s); \
} \ } \
return false; \ return false; \
} }
GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false) GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false) GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false) GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false) GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false) GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false) GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false) GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false) GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false) GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false) GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false) GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false) GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false) GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false) GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false) GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false) GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
/* /*
* The vector whole register store instructions are encoded similar to * The vector whole register store instructions are encoded similar to
* unmasked unit-stride store of elements with EEW=8. * unmasked unit-stride store of elements with EEW=8.
*/ */
GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true) GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true) GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true) GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true) GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
/* /*
*** Vector Integer Arithmetic Instructions *** Vector Integer Arithmetic Instructions