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target/riscv: Introduce privilege version field in the CSR ops.
To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. However, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra
Alistair Francis
parent
3a4af26d7a
commit
a4b2fa4331
2 changed files with 68 additions and 33 deletions
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@ -658,6 +658,8 @@ typedef struct {
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riscv_csr_op_fn op;
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riscv_csr_read128_fn read128;
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riscv_csr_write128_fn write128;
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/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
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uint32_t min_priv_ver;
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} riscv_csr_operations;
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/* CSR function table constants */
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@ -3070,13 +3070,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_FRM] = { "frm", fs, read_frm, write_frm },
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[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
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/* Vector CSRs */
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[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
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[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
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[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
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[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
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[CSR_VL] = { "vl", vs, read_vl },
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[CSR_VTYPE] = { "vtype", vs, read_vtype },
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[CSR_VLENB] = { "vlenb", vs, read_vlenb },
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[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VL] = { "vl", vs, read_vl,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VTYPE] = { "vtype", vs, read_vtype,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VLENB] = { "vlenb", vs, read_vlenb,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* User Timers and Counters */
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[CSR_CYCLE] = { "cycle", ctr, read_instret },
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[CSR_INSTRET] = { "instret", ctr, read_instret },
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@ -3185,33 +3192,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
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[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
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[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
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[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
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[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg },
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[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
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[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
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[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie },
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
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[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
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[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
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[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
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[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL },
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[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
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[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
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[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
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[CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie },
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[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
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[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
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[CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
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[CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
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[CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie ,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
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[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
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[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
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[CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
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@ -3245,7 +3277,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
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/* Physical Memory Protection */
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[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
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[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
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[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
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[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
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