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ppc patch queue for 2023-11-07:
This queue, the last one before the 8.2 feature freeze, has miscellanous changes that includes new PowerNV features and the new AmigaONE XE board. -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZUqiORYcZGFuaWVsaGI0 MTNAZ21haWwuY29tAAoJEDzZypbeAzFkBSUA/2qm8CyrRqY5+tsjtWQqZmPZ3L1F CgnXFNqtY2tzbTe5AQCi6FeQBEmXbZYVfryZyA+CQ4DUERc+18pe6hV3bBR9Cg== =cnHS -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into staging ppc patch queue for 2023-11-07: This queue, the last one before the 8.2 feature freeze, has miscellanous changes that includes new PowerNV features and the new AmigaONE XE board. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZUqiORYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFkBSUA/2qm8CyrRqY5+tsjtWQqZmPZ3L1F # CgnXFNqtY2tzbTe5AQCi6FeQBEmXbZYVfryZyA+CQ4DUERc+18pe6hV3bBR9Cg== # =cnHS # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu: ppc: qtest already exports qtest_rtas_call() hw/pci-host: Update PHB5 XSCOM registers ppc/pnv: Fix number of I2C engines and ports for power9/10 ppc/pnv: Connect PNV I2C controller to powernv10 ppc/pnv: Connect I2C controller model to powernv9 chip ppc/pnv: Add an I2C controller model tests/avocado: Add test for amigaone board hw/ppc: Add emulation of AmigaOne XE board hw/pci-host: Add emulation of Mai Logic Articia S Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
a3c3aaa846
21 changed files with 1414 additions and 38 deletions
17
include/hw/pci-host/articia.h
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17
include/hw/pci-host/articia.h
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@ -0,0 +1,17 @@
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/*
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* Mai Logic Articia S emulation
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*
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* Copyright (c) 2023 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#ifndef ARTICIA_H
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#define ARTICIA_H
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#define TYPE_ARTICIA "articia"
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#define TYPE_ARTICIA_PCI_HOST "articia-pci-host"
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#define TYPE_ARTICIA_PCI_BRIDGE "articia-pci-bridge"
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#endif
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@ -117,7 +117,7 @@ struct PnvPHB4 {
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MemoryRegion pci_regs_mr;
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/* Nest registers */
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#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17
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#define PHB4_PEC_NEST_STK_REGS_COUNT 0x18
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uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
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MemoryRegion nest_regs_mr;
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@ -77,10 +77,12 @@
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#define PEC_NEST_STK_BAR_EN_PHB PPC_BIT(2)
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#define PEC_NEST_STK_BAR_EN_INT PPC_BIT(3)
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#define PEC_NEST_STK_DATA_FRZ_TYPE 0x15
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#define PEC_NEST_STK_PBCQ_TUN_BAR 0x16
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#define PEC_NEST_STK_PBCQ_SPARSE_PAGE 0x16 /* P10 */
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#define PEC_NEST_STK_PBCQ_CACHE_INJ 0x17 /* P10 */
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/* XSCOM PCI global registers */
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#define PEC_PCI_PBAIB_HW_CONFIG 0x00
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#define PEC_PCI_PBAIB_HW_OVR 0x01
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#define PEC_PCI_PBAIB_READ_STK_OVR 0x02
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/* XSCOM PCI per-stack registers */
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@ -9,6 +9,7 @@
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_sbe.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_i2c.h"
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#include "hw/sysbus.h"
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OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
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@ -86,6 +87,9 @@ struct Pnv9Chip {
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#define PNV9_CHIP_MAX_PEC 3
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PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
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#define PNV9_CHIP_MAX_I2C 4
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PnvI2C i2c[PNV9_CHIP_MAX_I2C];
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};
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/*
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@ -115,6 +119,9 @@ struct Pnv10Chip {
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#define PNV10_CHIP_MAX_PEC 2
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PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
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#define PNV10_CHIP_MAX_I2C 4
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PnvI2C i2c[PNV10_CHIP_MAX_I2C];
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};
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#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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@ -130,6 +137,9 @@ struct PnvChipClass {
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uint32_t num_pecs;
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uint32_t num_phbs;
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uint32_t i2c_num_engines;
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const int *i2c_ports_per_engine;
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DeviceRealize parent_realize;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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38
include/hw/ppc/pnv_i2c.h
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38
include/hw/ppc/pnv_i2c.h
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@ -0,0 +1,38 @@
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/*
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* QEMU PowerPC PowerNV Processor I2C model
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*
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* Copyright (c) 2019-2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PPC_PNV_I2C_H
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#define PPC_PNV_I2C_H
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#include "hw/ppc/pnv.h"
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#include "hw/i2c/i2c.h"
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#include "qemu/fifo8.h"
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#define TYPE_PNV_I2C "pnv-i2c"
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#define PNV_I2C(obj) OBJECT_CHECK(PnvI2C, (obj), TYPE_PNV_I2C)
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#define PNV_I2C_REGS 0x20
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typedef struct PnvI2C {
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DeviceState parent;
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struct PnvChip *chip;
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qemu_irq psi_irq;
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uint64_t regs[PNV_I2C_REGS];
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uint32_t engine;
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uint32_t num_busses;
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I2CBus **busses;
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MemoryRegion xscom_regs;
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Fifo8 fifo;
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} PnvI2C;
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#endif /* PPC_PNV_I2C_H */
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@ -90,6 +90,9 @@ struct PnvXScomInterfaceClass {
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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#define PNV9_XSCOM_I2CM_BASE 0xa0000
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#define PNV9_XSCOM_I2CM_SIZE 0x1000
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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@ -149,6 +152,9 @@ struct PnvXScomInterfaceClass {
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#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
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#define PNV10_XSCOM_PSIHB_SIZE 0x100
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#define PNV10_XSCOM_I2CM_BASE PNV9_XSCOM_I2CM_BASE
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#define PNV10_XSCOM_I2CM_SIZE PNV9_XSCOM_I2CM_SIZE
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#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
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#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
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@ -1,10 +0,0 @@
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#ifndef HW_SPAPR_RTAS_H
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#define HW_SPAPR_RTAS_H
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/*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args,
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uint32_t nret, uint64_t rets);
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#endif /* HW_SPAPR_RTAS_H */
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