mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
Most of these are not modelled in QEMU, so save the overhead of calling a helper. The only exception is dczeroa. It assigns to hex_dczero_addr, which is handled during packet commit. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
This commit is contained in:
parent
111c529aa6
commit
a305a17039
2 changed files with 27 additions and 13 deletions
|
@ -659,20 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
|
|||
fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
|
||||
reg_field_info[FIELD].width, \
|
||||
reg_field_info[FIELD].offset)
|
||||
#define fBARRIER()
|
||||
#define fSYNCH()
|
||||
#define fISYNC()
|
||||
#define fDCFETCH(REG) \
|
||||
do { (void)REG; } while (0) /* Nothing to do in qemu */
|
||||
#define fICINVA(REG) \
|
||||
do { (void)REG; } while (0) /* Nothing to do in qemu */
|
||||
#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
|
||||
#define fDCCLEANA(REG) \
|
||||
do { (void)REG; } while (0) /* Nothing to do in qemu */
|
||||
#define fDCCLEANINVA(REG) \
|
||||
do { (void)REG; } while (0) /* Nothing to do in qemu */
|
||||
|
||||
#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
|
||||
#endif
|
||||
|
||||
#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
|
||||
STRBITNUM) /* Nothing */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue