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target/ppc: Add SMT support to time facilities

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The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a
per-core register. Add the necessary SMT synchronisation and value
sharing.

The TFMR can only drive the timebase state machine via thread 0 of the
core, which is almost certainly not right, but it is enough for skiboot
and certain other proprietary firmware.

Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-05-28 19:53:05 +10:00
parent d8c14411d0
commit a21d89b5f4
2 changed files with 136 additions and 11 deletions
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42
target/ppc/translate.c
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@ -247,13 +247,24 @@ static inline bool gen_serialize(DisasContext *ctx)
return true;
}
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
static inline bool gen_serialize_core(DisasContext *ctx)
{
if (ctx->flags & POWERPC_FLAG_SMT) {
return gen_serialize(ctx);
}
return true;
}
#endif
static inline bool gen_serialize_core_lpar(DisasContext *ctx)
{
#if defined(TARGET_PPC64)
if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
return gen_serialize(ctx);
}
#endif
return true;
}
#endif
@ -667,12 +678,20 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
#if !defined(CONFIG_USER_ONLY)
void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]);
}
void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]);
}
@ -696,6 +715,9 @@ void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_purr(tcg_env, cpu_gpr[gprn]);
}
@ -709,6 +731,9 @@ void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]);
}
@ -721,12 +746,18 @@ void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]);
}
void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core_lpar(ctx)) {
return;
}
translator_io_start(&ctx->base);
gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]);
}
@ -1220,11 +1251,18 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn)
{
/* Reading TFMR can cause it to be updated, so serialize threads here too */
if (!gen_serialize_core(ctx)) {
return;
}
gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env);
}
void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn)
{
if (!gen_serialize_core(ctx)) {
return;
}
gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]);
}