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target/arm: Implement SVE floating-point trig select coefficient

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:09 +01:00 • committed by Peter Maydell
parent 0762cd428f
commit a1f233f25f
4 changed files with 72 additions and 0 deletions
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21
target/arm/translate-sve.c
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@ -953,6 +953,27 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn)
return true;
}
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
static gen_helper_gvec_3 * const fns[4] = {
NULL,
gen_helper_sve_ftssel_h,
gen_helper_sve_ftssel_s,
gen_helper_sve_ftssel_d,
};
if (a->esz == 0) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, 0, fns[a->esz]);
}
return true;
}
/*
*** SVE Predicate Logical Operations Group
*/