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target/riscv: separation of bitwise logic and arithmetic helpers

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Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-06 22:00:55 +01:00 • committed by Alistair Francis
parent 344b4a82fc
commit a1a3aac448
3 changed files with 36 additions and 9 deletions
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6
target/riscv/insn_trans/trans_rvb.c.inc
View file

@ -86,19 +86,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
static bool trans_min(DisasContext *ctx, arg_min *a)

12
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -252,17 +252,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
@ -319,7 +319,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
return gen_logic(ctx, a, tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@ -334,12 +334,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
return gen_logic(ctx, a, tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
return gen_logic(ctx, a, tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)