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Hexagon: fix HVX store new
At 09a7e7db0f
(Hexagon (target/hexagon) Remove uses of
op_regs_generated.h.inc, 2024-03-06), we've changed the logic of
check_new_value() to use the new pre-calculated
packet->insn[...].dest_idx instead of calculating the index on the fly
using opcode_reginfo[...]. The dest_idx index is calculated roughly like
the following:
for reg in iset[tag]["syntax"]:
if reg.is_written():
dest_idx = regno
break
Thus, we take the first register that is writtable. Before that,
however, we also used to follow an alphabetical order on the register
type: 'd', 'e', 'x', and 'y'. No longer following that makes us select
the wrong register index and the HVX store new instruction does not
update the memory like expected.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Message-Id: <f548dc1c240819c724245e887f29f918441e9125.1716220379.git.quic_mathbern@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
This commit is contained in:
parent
3e246da2c3
commit
a1852002c7
2 changed files with 29 additions and 3 deletions
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@ -89,6 +89,7 @@ def gen_trans_funcs(f):
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new_read_idx = -1
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dest_idx = -1
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dest_idx_reg_id = None
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has_pred_dest = "false"
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for regno, (reg_type, reg_id, *_) in enumerate(regs):
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reg = hex_common.get_register(tag, reg_type, reg_id)
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@ -97,9 +98,11 @@ def gen_trans_funcs(f):
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"""))
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if reg.is_read() and reg.is_new():
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new_read_idx = regno
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# dest_idx should be the first destination, so check for -1
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if reg.is_written() and dest_idx == -1:
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dest_idx = regno
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if reg.is_written():
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# dest_idx should be the first destination alphabetically
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if dest_idx_reg_id is None or reg_id < dest_idx_reg_id:
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dest_idx = regno
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dest_idx_reg_id = reg_id
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if reg_type == "P" and reg.is_written() and not reg.is_read():
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has_pred_dest = "true"
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