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hw/arm/fsl-imx8mp: Add GPIO controllers

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-10-shentey@gmail.com
[PMM: drop static const from gpio_table for GCC 7.5]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow 2025-02-23 12:46:59 +01:00 • committed by Peter Maydell
parent fd1deb5301
commit a17c1d932e
3 changed files with 70 additions and 0 deletions
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1
docs/system/arm/imx8mp-evk.rst
View file

@ -14,6 +14,7 @@ The ``imx8mp-evk`` machine implements the following devices:
* 4 UARTs * 4 UARTs
* 3 USDHC Storage Controllers * 3 USDHC Storage Controllers
* 1 Designware PCI Express Controller * 1 Designware PCI Express Controller
* 5 GPIO Controllers
* Secure Non-Volatile Storage (SNVS) including an RTC * Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree * Clock Tree

55
hw/arm/fsl-imx8mp.c
View file

@ -208,6 +208,11 @@ static void fsl_imx8mp_init(Object *obj)
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
} }
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
g_autofree char *name = g_strdup_printf("usdhc%d", i + 1); g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
@ -355,6 +360,55 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(gicdev, serial_table[i].irq)); qdev_get_gpio_in(gicdev, serial_table[i].irq));
} }
/* GPIOs */
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
struct {
hwaddr addr;
unsigned int irq_low;
unsigned int irq_high;
} gpio_table[FSL_IMX8MP_NUM_GPIOS] = {
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr,
FSL_IMX8MP_GPIO1_LOW_IRQ,
FSL_IMX8MP_GPIO1_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr,
FSL_IMX8MP_GPIO2_LOW_IRQ,
FSL_IMX8MP_GPIO2_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr,
FSL_IMX8MP_GPIO3_LOW_IRQ,
FSL_IMX8MP_GPIO3_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr,
FSL_IMX8MP_GPIO4_LOW_IRQ,
FSL_IMX8MP_GPIO4_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr,
FSL_IMX8MP_GPIO5_LOW_IRQ,
FSL_IMX8MP_GPIO5_HIGH_IRQ
},
};
object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
true, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
}
/* USDHCs */ /* USDHCs */
for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
struct { struct {
@ -415,6 +469,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
case FSL_IMX8MP_CCM: case FSL_IMX8MP_CCM:
case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_DIST:
case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GIC_REDIST:
case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE1:
case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_PCIE_PHY1:
case FSL_IMX8MP_RAM: case FSL_IMX8MP_RAM:

14
include/hw/arm/fsl-imx8mp.h
View file

@ -11,6 +11,7 @@
#include "cpu.h" #include "cpu.h"
#include "hw/char/imx_serial.h" #include "hw/char/imx_serial.h"
#include "hw/gpio/imx_gpio.h"
#include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_common.h"
#include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_analog.h"
@ -29,6 +30,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
enum FslImx8mpConfiguration { enum FslImx8mpConfiguration {
FSL_IMX8MP_NUM_CPUS = 4, FSL_IMX8MP_NUM_CPUS = 4,
FSL_IMX8MP_NUM_GPIOS = 5,
FSL_IMX8MP_NUM_IRQS = 160, FSL_IMX8MP_NUM_IRQS = 160,
FSL_IMX8MP_NUM_UARTS = 4, FSL_IMX8MP_NUM_UARTS = 4,
FSL_IMX8MP_NUM_USDHCS = 3, FSL_IMX8MP_NUM_USDHCS = 3,
@ -39,6 +41,7 @@ struct FslImx8mpState {
ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
GICv3State gic; GICv3State gic;
IMXGPIOState gpio[FSL_IMX8MP_NUM_GPIOS];
IMX8MPCCMState ccm; IMX8MPCCMState ccm;
IMX8MPAnalogState analog; IMX8MPAnalogState analog;
IMX7SNVSState snvs; IMX7SNVSState snvs;
@ -202,6 +205,17 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_UART5_IRQ = 30, FSL_IMX8MP_UART5_IRQ = 30,
FSL_IMX8MP_UART6_IRQ = 16, FSL_IMX8MP_UART6_IRQ = 16,
FSL_IMX8MP_GPIO1_LOW_IRQ = 64,
FSL_IMX8MP_GPIO1_HIGH_IRQ = 65,
FSL_IMX8MP_GPIO2_LOW_IRQ = 66,
FSL_IMX8MP_GPIO2_HIGH_IRQ = 67,
FSL_IMX8MP_GPIO3_LOW_IRQ = 68,
FSL_IMX8MP_GPIO3_HIGH_IRQ = 69,
FSL_IMX8MP_GPIO4_LOW_IRQ = 70,
FSL_IMX8MP_GPIO4_HIGH_IRQ = 71,
FSL_IMX8MP_GPIO5_LOW_IRQ = 72,
FSL_IMX8MP_GPIO5_HIGH_IRQ = 73,
FSL_IMX8MP_PCI_INTA_IRQ = 126, FSL_IMX8MP_PCI_INTA_IRQ = 126,
FSL_IMX8MP_PCI_INTB_IRQ = 125, FSL_IMX8MP_PCI_INTB_IRQ = 125,
FSL_IMX8MP_PCI_INTC_IRQ = 124, FSL_IMX8MP_PCI_INTC_IRQ = 124,