motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 08:43:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/arm/fsl-imx8mp: Add GPIO controllers

Browse source 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-10-shentey@gmail.com
[PMM: drop static const from gpio_table for GCC 7.5]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow 2025-02-23 12:46:59 +01:00 • committed by Peter Maydell
parent fd1deb5301
commit a17c1d932e
3 changed files with 70 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

55
hw/arm/fsl-imx8mp.c
View file

@ -208,6 +208,11 @@ static void fsl_imx8mp_init(Object *obj)
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
@ -355,6 +360,55 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(gicdev, serial_table[i].irq));
}
/* GPIOs */
for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
struct {
hwaddr addr;
unsigned int irq_low;
unsigned int irq_high;
} gpio_table[FSL_IMX8MP_NUM_GPIOS] = {
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr,
FSL_IMX8MP_GPIO1_LOW_IRQ,
FSL_IMX8MP_GPIO1_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr,
FSL_IMX8MP_GPIO2_LOW_IRQ,
FSL_IMX8MP_GPIO2_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr,
FSL_IMX8MP_GPIO3_LOW_IRQ,
FSL_IMX8MP_GPIO3_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr,
FSL_IMX8MP_GPIO4_LOW_IRQ,
FSL_IMX8MP_GPIO4_HIGH_IRQ
},
{
fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr,
FSL_IMX8MP_GPIO5_LOW_IRQ,
FSL_IMX8MP_GPIO5_HIGH_IRQ
},
};
object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
true, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
}
/* USDHCs */
for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
struct {
@ -415,6 +469,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
case FSL_IMX8MP_CCM:
case FSL_IMX8MP_GIC_DIST:
case FSL_IMX8MP_GIC_REDIST:
case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
case FSL_IMX8MP_PCIE1:
case FSL_IMX8MP_PCIE_PHY1:
case FSL_IMX8MP_RAM: