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target-arm queue:

Browse source 
* Implement FEAT_ECV
  * STM32L4x5: Implement GPIO device
  * Fix 32-bit SMOPA
  * Refactor v7m related code from cpu32.c into its own file
  * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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Merge tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Implement FEAT_ECV
 * STM32L4x5: Implement GPIO device
 * Fix 32-bit SMOPA
 * Refactor v7m related code from cpu32.c into its own file
 * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

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# gpg: Signature made Fri 08 Mar 2024 15:49:49 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Move v7m-related code from cpu32.c into a separate file
  hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
  target/arm: Fix 32-bit SMOPA
  tests/qtest: Add STM32L4x5 GPIO QTest testcase
  hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
  hw/gpio: Implement STM32L4x5 GPIO
  target/arm: Enable FEAT_ECV for 'max' CPU
  target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
  target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
  target/arm: Implement new FEAT_ECV trap bits
  target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
  target/arm: use FIELD macro for CNTHCTL bit definitions
  target/arm: Timer _EL02 registers UNDEF for E2H == 0
  target/arm: Move some register related defines to internals.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-03-08 18:19:09 +00:00
commit a146c6f88c
31 changed files with 1962 additions and 456 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/arm/stm32l4x5_soc.h
View file

@ -30,6 +30,7 @@
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "hw/misc/stm32l4x5_rcc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "qom/object.h"
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
@ -49,6 +50,7 @@ struct Stm32l4x5SocState {
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
Stm32l4x5SyscfgState syscfg;
Stm32l4x5RccState rcc;
Stm32l4x5GpioState gpio[NUM_GPIOS];
MemoryRegion sram1;
MemoryRegion sram2;

71
include/hw/gpio/stm32l4x5_gpio.h Normal file
View file

@ -0,0 +1,71 @@
/*
* STM32L4x5 GPIO (General Purpose Input/Ouput)
*
* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
/*
* The reference used is the STMicroElectronics RM0351 Reference manual
* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
* https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
*/
#ifndef HW_STM32L4X5_GPIO_H
#define HW_STM32L4X5_GPIO_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
#define NUM_GPIOS 8
#define GPIO_NUM_PINS 16
struct Stm32l4x5GpioState {
SysBusDevice parent_obj;
MemoryRegion mmio;
/* GPIO registers */
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t idr;
uint32_t odr;
uint32_t lckr;
uint32_t afrl;
uint32_t afrh;
uint32_t ascr;
/* GPIO registers reset values */
uint32_t moder_reset;
uint32_t ospeedr_reset;
uint32_t pupdr_reset;
/*
* External driving of pins.
* The pins can be set externally through the device
* anonymous input GPIOs lines under certain conditions.
* The pin must not be in push-pull output mode,
* and can't be set high in open-drain mode.
* Pins driven externally and configured to
* output mode will in general be "disconnected"
* (see `get_gpio_pinmask_to_disconnect()`)
*/
uint16_t disconnected_pins;
uint16_t pins_connected_high;
char *name;
Clock *clk;
qemu_irq pin[GPIO_NUM_PINS];
};
#endif

3
include/hw/misc/stm32l4x5_syscfg.h
View file

@ -26,12 +26,11 @@
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
#define NUM_GPIOS 8
#define GPIO_NUM_PINS 16
#define SYSCFG_NUM_EXTICR 4
struct Stm32l4x5SyscfgState {

2
include/hw/rtc/sun4v-rtc.h
View file

@ -5,7 +5,7 @@
*
* Copyright (c) 2016 Artyom Tarasenko
*
* This code is licensed under the GNU GPL v3 or (at your option) any later
* This code is licensed under the GNU GPL v2 or (at your option) any later
* version.
*/