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target-ppc: QOM'ify CPU reset
Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
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6cca7ad686
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3 changed files with 47 additions and 46 deletions
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@ -10211,10 +10211,54 @@ static void ppc_cpu_reset(CPUState *s)
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PowerPCCPU *cpu = POWERPC_CPU(s);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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target_ulong msr;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, 0);
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}
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pcc->parent_reset(s);
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cpu_state_reset(env);
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msr = (target_ulong)0;
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if (0) {
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/* XXX: find a suitable condition to enable the hypervisor mode */
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msr |= (target_ulong)MSR_HVB;
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}
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msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
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msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
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msr |= (target_ulong)1 << MSR_EP;
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#if defined(DO_SINGLE_STEP) && 0
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/* Single step trace mode */
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msr |= (target_ulong)1 << MSR_SE;
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msr |= (target_ulong)1 << MSR_BE;
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#endif
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#if defined(CONFIG_USER_ONLY)
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msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
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msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
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msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
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msr |= (target_ulong)1 << MSR_PR;
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#else
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env->excp_prefix = env->hreset_excp_prefix;
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env->nip = env->hreset_vector | env->excp_prefix;
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if (env->mmu_model != POWERPC_MMU_REAL) {
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ppc_tlb_invalidate_all(env);
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}
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#endif
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env->msr = msr & env->msr_mask;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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env->msr |= (1ULL << MSR_SF);
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}
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#endif
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hreg_compute_hflags(env);
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env->reserve_addr = (target_ulong)-1ULL;
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/* Be sure no exception or interrupt is pending */
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env->pending_interrupts = 0;
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env->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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/* Flush all TLBs */
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tlb_flush(env, 1);
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}
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static void ppc_cpu_initfn(Object *obj)
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