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target/riscv: Add rev8 instruction, removing grev/grevi

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The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.

This commit adds the new rev8 instruction and removes grev/grevi.

Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:13 +02:00 • committed by Alistair Francis
parent 7e68e6c79b
commit a1095bdcb0
4 changed files with 15 additions and 79 deletions
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40
target/riscv/bitmanip_helper.c
View file

@ -24,46 +24,6 @@
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
static const uint64_t adjacent_masks[] = {
dup_const(MO_8, 0x55),
dup_const(MO_8, 0x33),
dup_const(MO_8, 0x0f),
dup_const(MO_16, 0xff),
dup_const(MO_32, 0xffff),
UINT32_MAX
};
static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
{
return ((x & mask) << shift) | ((x & ~mask) >> shift);
}
static target_ulong do_grev(target_ulong rs1,
target_ulong rs2,
int bits)
{
target_ulong x = rs1;
int i, shift;
for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
if (rs2 & shift) {
x = do_swap(x, adjacent_masks[i], shift);
}
}
return x;
}
target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, TARGET_LONG_BITS);
}
target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, 32);
}
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;