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hw/ssi: Fix Linux driver init issue with xilinx_spi

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The problem is that the Linux driver expects the master transaction inhibit
bit(R_SPICR_MTI) to be set during driver initialization so that it can
detect the fifo size but QEMU defaults it to zero out of reset.  The
datasheet indicates this bit is active on reset.

See page 25, SPI Control Register section:
https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf

Signed-off-by: Chris Rauer <crauer@google.com>
Message-id: 20230323182811.2641044-1-crauer@google.com
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Chris Rauer 2023-04-03 16:12:30 +01:00 • committed by Peter Maydell
parent 782781e85d
commit a0eaa126af
1 changed files with 1 additions and 0 deletions
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hw/ssi/xilinx_spi.c
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@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s)
txfifo_reset(s);
s->regs[R_SPISSR] = ~0;
s->regs[R_SPICR] = R_SPICR_MTI;
xlx_spi_update_irq(s);
xlx_spi_update_cs(s);
}