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cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber
parent
19a77215f1
commit
a0e372f0c4
18 changed files with 66 additions and 65 deletions
83
gdbstub.c
83
gdbstub.c
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@ -530,8 +530,6 @@ static const int gpr_map[16] = {
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#endif
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static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
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#define IDX_IP_REG CPU_NB_REGS
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#define IDX_FLAGS_REG (IDX_IP_REG + 1)
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#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
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@ -732,7 +730,6 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
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historical mishap the FP registers appear in between core integer
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regs and PC, MSR, CR, and so forth. We hack round this by giving the
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FP regs zero size when talking to a newer gdb. */
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#define NUM_CORE_REGS 71
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#if defined (TARGET_PPC64)
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#define GDB_CORE_XML "power64-core.xml"
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#else
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@ -837,12 +834,6 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
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#elif defined (TARGET_SPARC)
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#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
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#define NUM_CORE_REGS 86
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#else
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#define NUM_CORE_REGS 72
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#endif
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#ifdef TARGET_ABI32
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#define GET_REGA(val) GET_REG32(val)
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#else
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@ -1030,7 +1021,6 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
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the FPA registers appear in between core integer regs and the CPSR.
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We hack round this by giving the FPA regs zero size when talking to a
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newer gdb. */
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#define NUM_CORE_REGS 26
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#define GDB_CORE_XML "arm-core.xml"
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static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
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@ -1104,8 +1094,6 @@ static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
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#elif defined (TARGET_M68K)
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#define NUM_CORE_REGS 18
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#define GDB_CORE_XML "cf-core.xml"
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static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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@ -1157,8 +1145,6 @@ static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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}
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#elif defined (TARGET_MIPS)
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#define NUM_CORE_REGS 73
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static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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@ -1285,8 +1271,6 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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}
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#elif defined(TARGET_OPENRISC)
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#define NUM_CORE_REGS (32 + 3)
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static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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@ -1312,9 +1296,11 @@ static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUOpenRISCState *env,
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uint8_t *mem_buf, int n)
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{
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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uint32_t tmp;
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if (n > NUM_CORE_REGS) {
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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@ -1347,8 +1333,6 @@ static int cpu_gdb_write_register(CPUOpenRISCState *env,
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/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
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/* FIXME: We should use XML for this. */
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#define NUM_CORE_REGS 59
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static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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switch (n) {
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@ -1465,8 +1449,6 @@ static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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}
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#elif defined (TARGET_MICROBLAZE)
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#define NUM_CORE_REGS (32 + 5)
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static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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@ -1479,9 +1461,11 @@ static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = mb_env_get_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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uint32_t tmp;
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if (n > NUM_CORE_REGS) {
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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@ -1496,8 +1480,6 @@ static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
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}
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#elif defined (TARGET_CRIS)
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#define NUM_CORE_REGS 49
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static int
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read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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@ -1605,8 +1587,6 @@ static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
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}
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#elif defined (TARGET_ALPHA)
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#define NUM_CORE_REGS 67
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static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
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{
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uint64_t val;
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@ -1675,8 +1655,6 @@ static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
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}
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#elif defined (TARGET_S390X)
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#define NUM_CORE_REGS S390_NUM_REGS
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static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
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{
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uint64_t val;
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@ -1740,7 +1718,6 @@ static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
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#elif defined (TARGET_LM32)
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#include "hw/lm32/lm32_pic.h"
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#define NUM_CORE_REGS (32 + 7)
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static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
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{
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@ -1770,9 +1747,11 @@ static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
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{
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LM32CPU *cpu = lm32_env_get_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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uint32_t tmp;
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if (n > NUM_CORE_REGS) {
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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@ -1806,14 +1785,6 @@ static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
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}
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#elif defined(TARGET_XTENSA)
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/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
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* Use num_regs to see all registers. gdb modification is required for that:
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* reset bit 0 in the 'flags' field of the registers definitions in the
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* gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
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*/
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#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
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#define num_g_regs NUM_CORE_REGS
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static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
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{
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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@ -1896,8 +1867,6 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
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}
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#else
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#define NUM_CORE_REGS 0
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static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
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{
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return 0;
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@ -1910,10 +1879,6 @@ static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
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#endif
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#if !defined(TARGET_XTENSA)
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static int num_g_regs = NUM_CORE_REGS;
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#endif
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#ifdef GDB_CORE_XML
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/* Encode data using the encoding for 'x' packets. */
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static int memtox(char *buf, const char *mem, int len)
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@ -1982,11 +1947,13 @@ static const char *get_feature_xml(const char *p, const char **newp)
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static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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CPUArchState *env = cpu->env_ptr;
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GDBRegisterState *r;
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if (reg < NUM_CORE_REGS)
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if (reg < cc->gdb_num_core_regs) {
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return cpu_gdb_read_register(env, mem_buf, reg);
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}
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for (r = cpu->gdb_regs; r; r = r->next) {
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if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
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@ -1998,11 +1965,13 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
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static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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CPUArchState *env = cpu->env_ptr;
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GDBRegisterState *r;
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if (reg < NUM_CORE_REGS)
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if (reg < cc->gdb_num_core_regs) {
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return cpu_gdb_write_register(env, mem_buf, reg);
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}
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for (r = cpu->gdb_regs; r; r = r->next) {
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if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
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@ -2012,7 +1981,6 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
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return 0;
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}
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#if !defined(TARGET_XTENSA)
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/* Register a supplemental set of CPU registers. If g_pos is nonzero it
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specifies the first register number and these registers are included in
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a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
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@ -2025,7 +1993,6 @@ void gdb_register_coprocessor(CPUState *cpu,
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{
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GDBRegisterState *s;
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GDBRegisterState **p;
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static int last_reg = NUM_CORE_REGS;
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p = &cpu->gdb_regs;
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while (*p) {
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@ -2036,25 +2003,22 @@ void gdb_register_coprocessor(CPUState *cpu,
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}
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s = g_new0(GDBRegisterState, 1);
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s->base_reg = last_reg;
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s->base_reg = cpu->gdb_num_regs;
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s->num_regs = num_regs;
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s->get_reg = get_reg;
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s->set_reg = set_reg;
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s->xml = xml;
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/* Add to end of list. */
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last_reg += num_regs;
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cpu->gdb_num_regs += num_regs;
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*p = s;
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if (g_pos) {
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if (g_pos != s->base_reg) {
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fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
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"Expected %d got %d\n", xml, g_pos, s->base_reg);
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} else {
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num_g_regs = last_reg;
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}
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}
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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static const int xlat_gdb_type[] = {
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@ -2184,9 +2148,6 @@ static CPUState *find_cpu(uint32_t thread_id)
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static int gdb_handle_packet(GDBState *s, const char *line_buf)
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{
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#ifdef TARGET_XTENSA
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CPUArchState *env;
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#endif
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CPUState *cpu;
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const char *p;
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uint32_t thread;
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@ -2334,11 +2295,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
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break;
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case 'g':
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cpu_synchronize_state(s->g_cpu);
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#ifdef TARGET_XTENSA
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env = s->g_cpu->env_ptr;
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#endif
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len = 0;
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for (addr = 0; addr < num_g_regs; addr++) {
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for (addr = 0; addr < s->g_cpu->gdb_num_regs; addr++) {
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reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
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len += reg_size;
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}
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@ -2347,13 +2305,10 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
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break;
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case 'G':
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cpu_synchronize_state(s->g_cpu);
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#ifdef TARGET_XTENSA
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env = s->g_cpu->env_ptr;
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#endif
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registers = mem_buf;
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len = strlen(p) / 2;
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hextomem((uint8_t *)registers, p, len);
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for (addr = 0; addr < num_g_regs && len > 0; addr++) {
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for (addr = 0; addr < s->g_cpu->gdb_num_regs && len > 0; addr++) {
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reg_size = gdb_write_register(s->g_cpu, registers, addr);
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len -= reg_size;
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registers += reg_size;
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