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hw/display: fix tab indentation
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <5cefd05b4d3721d416e48e6df19df18cb6338933.1666707782.git.amarjargal16@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Amarjargal Gundjalam
Thomas Huth
parent
ef99aa2a31
commit
a076a3dcbf
6 changed files with 1499 additions and 1499 deletions
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@ -182,25 +182,25 @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
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}
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switch (addr) {
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case 0x00: /* DSS_REVISIONNUMBER */
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case 0x00: /* DSS_REVISIONNUMBER */
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return 0x20;
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case 0x10: /* DSS_SYSCONFIG */
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case 0x10: /* DSS_SYSCONFIG */
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return s->autoidle;
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case 0x14: /* DSS_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x14: /* DSS_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x40: /* DSS_CONTROL */
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case 0x40: /* DSS_CONTROL */
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return s->control;
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case 0x50: /* DSS_PSA_LCD_REG_1 */
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case 0x54: /* DSS_PSA_LCD_REG_2 */
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case 0x58: /* DSS_PSA_VIDEO_REG */
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case 0x50: /* DSS_PSA_LCD_REG_1 */
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case 0x54: /* DSS_PSA_LCD_REG_2 */
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case 0x58: /* DSS_PSA_VIDEO_REG */
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/* TODO: fake some values when appropriate s->control bits are set */
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return 0;
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case 0x5c: /* DSS_STATUS */
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case 0x5c: /* DSS_STATUS */
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return 1 + (s->control & 1);
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default:
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@ -221,22 +221,22 @@ static void omap_diss_write(void *opaque, hwaddr addr,
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}
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switch (addr) {
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case 0x00: /* DSS_REVISIONNUMBER */
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case 0x14: /* DSS_SYSSTATUS */
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case 0x50: /* DSS_PSA_LCD_REG_1 */
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case 0x54: /* DSS_PSA_LCD_REG_2 */
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case 0x58: /* DSS_PSA_VIDEO_REG */
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case 0x5c: /* DSS_STATUS */
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case 0x00: /* DSS_REVISIONNUMBER */
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case 0x14: /* DSS_SYSSTATUS */
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case 0x50: /* DSS_PSA_LCD_REG_1 */
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case 0x54: /* DSS_PSA_LCD_REG_2 */
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case 0x58: /* DSS_PSA_VIDEO_REG */
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case 0x5c: /* DSS_STATUS */
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OMAP_RO_REG(addr);
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break;
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case 0x10: /* DSS_SYSCONFIG */
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if (value & 2) /* SOFTRESET */
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case 0x10: /* DSS_SYSCONFIG */
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if (value & 2) /* SOFTRESET */
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omap_dss_reset(s);
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s->autoidle = value & 1;
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break;
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case 0x40: /* DSS_CONTROL */
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case 0x40: /* DSS_CONTROL */
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s->control = value & 0x3dd;
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break;
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@ -261,112 +261,112 @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
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}
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switch (addr) {
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case 0x000: /* DISPC_REVISION */
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case 0x000: /* DISPC_REVISION */
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return 0x20;
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case 0x010: /* DISPC_SYSCONFIG */
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case 0x010: /* DISPC_SYSCONFIG */
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return s->dispc.idlemode;
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case 0x014: /* DISPC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x014: /* DISPC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x018: /* DISPC_IRQSTATUS */
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case 0x018: /* DISPC_IRQSTATUS */
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return s->dispc.irqst;
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case 0x01c: /* DISPC_IRQENABLE */
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case 0x01c: /* DISPC_IRQENABLE */
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return s->dispc.irqen;
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case 0x040: /* DISPC_CONTROL */
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case 0x040: /* DISPC_CONTROL */
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return s->dispc.control;
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case 0x044: /* DISPC_CONFIG */
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case 0x044: /* DISPC_CONFIG */
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return s->dispc.config;
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case 0x048: /* DISPC_CAPABLE */
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case 0x048: /* DISPC_CAPABLE */
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return s->dispc.capable;
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case 0x04c: /* DISPC_DEFAULT_COLOR0 */
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case 0x04c: /* DISPC_DEFAULT_COLOR0 */
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return s->dispc.bg[0];
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case 0x050: /* DISPC_DEFAULT_COLOR1 */
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case 0x050: /* DISPC_DEFAULT_COLOR1 */
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return s->dispc.bg[1];
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case 0x054: /* DISPC_TRANS_COLOR0 */
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case 0x054: /* DISPC_TRANS_COLOR0 */
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return s->dispc.trans[0];
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case 0x058: /* DISPC_TRANS_COLOR1 */
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case 0x058: /* DISPC_TRANS_COLOR1 */
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return s->dispc.trans[1];
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case 0x05c: /* DISPC_LINE_STATUS */
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case 0x05c: /* DISPC_LINE_STATUS */
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return 0x7ff;
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case 0x060: /* DISPC_LINE_NUMBER */
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case 0x060: /* DISPC_LINE_NUMBER */
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return s->dispc.line;
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case 0x064: /* DISPC_TIMING_H */
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case 0x064: /* DISPC_TIMING_H */
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return s->dispc.timing[0];
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case 0x068: /* DISPC_TIMING_V */
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case 0x068: /* DISPC_TIMING_V */
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return s->dispc.timing[1];
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case 0x06c: /* DISPC_POL_FREQ */
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case 0x06c: /* DISPC_POL_FREQ */
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return s->dispc.timing[2];
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case 0x070: /* DISPC_DIVISOR */
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case 0x070: /* DISPC_DIVISOR */
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return s->dispc.timing[3];
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case 0x078: /* DISPC_SIZE_DIG */
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case 0x078: /* DISPC_SIZE_DIG */
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return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);
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case 0x07c: /* DISPC_SIZE_LCD */
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case 0x07c: /* DISPC_SIZE_LCD */
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return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);
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case 0x080: /* DISPC_GFX_BA0 */
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case 0x080: /* DISPC_GFX_BA0 */
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return s->dispc.l[0].addr[0];
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case 0x084: /* DISPC_GFX_BA1 */
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case 0x084: /* DISPC_GFX_BA1 */
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return s->dispc.l[0].addr[1];
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case 0x088: /* DISPC_GFX_POSITION */
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case 0x088: /* DISPC_GFX_POSITION */
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return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;
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case 0x08c: /* DISPC_GFX_SIZE */
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case 0x08c: /* DISPC_GFX_SIZE */
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return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);
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case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
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case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
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return s->dispc.l[0].attr;
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case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
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case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
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return s->dispc.l[0].tresh;
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case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
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case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
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return 256;
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case 0x0ac: /* DISPC_GFX_ROW_INC */
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case 0x0ac: /* DISPC_GFX_ROW_INC */
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return s->dispc.l[0].rowinc;
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case 0x0b0: /* DISPC_GFX_PIXEL_INC */
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case 0x0b0: /* DISPC_GFX_PIXEL_INC */
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return s->dispc.l[0].colinc;
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case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
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case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
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return s->dispc.l[0].wininc;
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case 0x0b8: /* DISPC_GFX_TABLE_BA */
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case 0x0b8: /* DISPC_GFX_TABLE_BA */
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return s->dispc.l[0].addr[2];
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case 0x0bc: /* DISPC_VID1_BA0 */
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case 0x0c0: /* DISPC_VID1_BA1 */
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case 0x0c4: /* DISPC_VID1_POSITION */
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case 0x0c8: /* DISPC_VID1_SIZE */
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case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
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case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
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case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
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case 0x0d8: /* DISPC_VID1_ROW_INC */
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case 0x0dc: /* DISPC_VID1_PIXEL_INC */
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case 0x0e0: /* DISPC_VID1_FIR */
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case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
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case 0x0e8: /* DISPC_VID1_ACCU0 */
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case 0x0ec: /* DISPC_VID1_ACCU1 */
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case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
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case 0x14c: /* DISPC_VID2_BA0 */
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case 0x150: /* DISPC_VID2_BA1 */
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case 0x154: /* DISPC_VID2_POSITION */
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case 0x158: /* DISPC_VID2_SIZE */
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case 0x15c: /* DISPC_VID2_ATTRIBUTES */
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case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
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case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
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case 0x168: /* DISPC_VID2_ROW_INC */
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case 0x16c: /* DISPC_VID2_PIXEL_INC */
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case 0x170: /* DISPC_VID2_FIR */
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case 0x174: /* DISPC_VID2_PICTURE_SIZE */
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case 0x178: /* DISPC_VID2_ACCU0 */
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case 0x17c: /* DISPC_VID2_ACCU1 */
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case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
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case 0x1d4: /* DISPC_DATA_CYCLE1 */
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case 0x1d8: /* DISPC_DATA_CYCLE2 */
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case 0x1dc: /* DISPC_DATA_CYCLE3 */
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case 0x0bc: /* DISPC_VID1_BA0 */
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case 0x0c0: /* DISPC_VID1_BA1 */
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case 0x0c4: /* DISPC_VID1_POSITION */
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case 0x0c8: /* DISPC_VID1_SIZE */
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case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
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case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
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case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
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case 0x0d8: /* DISPC_VID1_ROW_INC */
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case 0x0dc: /* DISPC_VID1_PIXEL_INC */
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case 0x0e0: /* DISPC_VID1_FIR */
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case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
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case 0x0e8: /* DISPC_VID1_ACCU0 */
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case 0x0ec: /* DISPC_VID1_ACCU1 */
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case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
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case 0x14c: /* DISPC_VID2_BA0 */
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case 0x150: /* DISPC_VID2_BA1 */
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case 0x154: /* DISPC_VID2_POSITION */
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case 0x158: /* DISPC_VID2_SIZE */
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case 0x15c: /* DISPC_VID2_ATTRIBUTES */
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case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
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case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
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case 0x168: /* DISPC_VID2_ROW_INC */
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case 0x16c: /* DISPC_VID2_PIXEL_INC */
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case 0x170: /* DISPC_VID2_FIR */
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case 0x174: /* DISPC_VID2_PICTURE_SIZE */
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case 0x178: /* DISPC_VID2_ACCU0 */
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case 0x17c: /* DISPC_VID2_ACCU1 */
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case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
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case 0x1d4: /* DISPC_DATA_CYCLE1 */
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case 0x1d8: /* DISPC_DATA_CYCLE2 */
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case 0x1dc: /* DISPC_DATA_CYCLE3 */
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return 0;
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default:
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@ -387,33 +387,33 @@ static void omap_disc_write(void *opaque, hwaddr addr,
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}
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switch (addr) {
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case 0x010: /* DISPC_SYSCONFIG */
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if (value & 2) /* SOFTRESET */
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case 0x010: /* DISPC_SYSCONFIG */
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if (value & 2) /* SOFTRESET */
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omap_dss_reset(s);
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s->dispc.idlemode = value & 0x301b;
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break;
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case 0x018: /* DISPC_IRQSTATUS */
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case 0x018: /* DISPC_IRQSTATUS */
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s->dispc.irqst &= ~value;
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omap_dispc_interrupt_update(s);
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break;
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case 0x01c: /* DISPC_IRQENABLE */
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case 0x01c: /* DISPC_IRQENABLE */
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s->dispc.irqen = value & 0xffff;
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omap_dispc_interrupt_update(s);
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break;
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case 0x040: /* DISPC_CONTROL */
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case 0x040: /* DISPC_CONTROL */
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s->dispc.control = value & 0x07ff9fff;
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s->dig.enable = (value >> 1) & 1;
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s->lcd.enable = (value >> 0) & 1;
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if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
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if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
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if (!((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) {
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fprintf(stderr, "%s: Overlay Optimization when no overlay "
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"region effectively exists leads to "
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"unpredictable behaviour!\n", __func__);
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}
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if (value & (1 << 6)) { /* GODIGITAL */
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if (value & (1 << 6)) { /* GODIGITAL */
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/* XXX: Shadowed fields are:
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* s->dispc.config
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* s->dispc.capable
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@ -444,13 +444,13 @@ static void omap_disc_write(void *opaque, hwaddr addr,
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* All they need to be loaded here from their shadow registers.
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*/
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}
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if (value & (1 << 5)) { /* GOLCD */
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if (value & (1 << 5)) { /* GOLCD */
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/* XXX: Likewise for LCD here. */
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}
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s->dispc.invalidate = 1;
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break;
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case 0x044: /* DISPC_CONFIG */
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case 0x044: /* DISPC_CONFIG */
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s->dispc.config = value & 0x3fff;
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/* XXX:
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* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
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@ -459,73 +459,73 @@ static void omap_disc_write(void *opaque, hwaddr addr,
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s->dispc.invalidate = 1;
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break;
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case 0x048: /* DISPC_CAPABLE */
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case 0x048: /* DISPC_CAPABLE */
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s->dispc.capable = value & 0x3ff;
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break;
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case 0x04c: /* DISPC_DEFAULT_COLOR0 */
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case 0x04c: /* DISPC_DEFAULT_COLOR0 */
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s->dispc.bg[0] = value & 0xffffff;
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s->dispc.invalidate = 1;
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break;
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case 0x050: /* DISPC_DEFAULT_COLOR1 */
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case 0x050: /* DISPC_DEFAULT_COLOR1 */
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s->dispc.bg[1] = value & 0xffffff;
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s->dispc.invalidate = 1;
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break;
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case 0x054: /* DISPC_TRANS_COLOR0 */
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case 0x054: /* DISPC_TRANS_COLOR0 */
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s->dispc.trans[0] = value & 0xffffff;
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s->dispc.invalidate = 1;
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break;
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case 0x058: /* DISPC_TRANS_COLOR1 */
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case 0x058: /* DISPC_TRANS_COLOR1 */
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s->dispc.trans[1] = value & 0xffffff;
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s->dispc.invalidate = 1;
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break;
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case 0x060: /* DISPC_LINE_NUMBER */
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case 0x060: /* DISPC_LINE_NUMBER */
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s->dispc.line = value & 0x7ff;
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break;
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case 0x064: /* DISPC_TIMING_H */
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case 0x064: /* DISPC_TIMING_H */
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s->dispc.timing[0] = value & 0x0ff0ff3f;
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break;
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case 0x068: /* DISPC_TIMING_V */
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case 0x068: /* DISPC_TIMING_V */
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s->dispc.timing[1] = value & 0x0ff0ff3f;
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break;
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case 0x06c: /* DISPC_POL_FREQ */
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case 0x06c: /* DISPC_POL_FREQ */
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s->dispc.timing[2] = value & 0x0003ffff;
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break;
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case 0x070: /* DISPC_DIVISOR */
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case 0x070: /* DISPC_DIVISOR */
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s->dispc.timing[3] = value & 0x00ff00ff;
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break;
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case 0x078: /* DISPC_SIZE_DIG */
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s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
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s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
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case 0x078: /* DISPC_SIZE_DIG */
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s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
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s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
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s->dispc.invalidate = 1;
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break;
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case 0x07c: /* DISPC_SIZE_LCD */
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s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
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s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
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case 0x07c: /* DISPC_SIZE_LCD */
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s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
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s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
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s->dispc.invalidate = 1;
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break;
|
||||
case 0x080: /* DISPC_GFX_BA0 */
|
||||
case 0x080: /* DISPC_GFX_BA0 */
|
||||
s->dispc.l[0].addr[0] = (hwaddr) value;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x084: /* DISPC_GFX_BA1 */
|
||||
case 0x084: /* DISPC_GFX_BA1 */
|
||||
s->dispc.l[0].addr[1] = (hwaddr) value;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x088: /* DISPC_GFX_POSITION */
|
||||
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
|
||||
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
|
||||
case 0x088: /* DISPC_GFX_POSITION */
|
||||
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
|
||||
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x08c: /* DISPC_GFX_SIZE */
|
||||
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
|
||||
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
|
||||
case 0x08c: /* DISPC_GFX_SIZE */
|
||||
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
|
||||
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
|
||||
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
|
||||
s->dispc.l[0].attr = value & 0x7ff;
|
||||
if (value & (3 << 9))
|
||||
fprintf(stderr, "%s: Big-endian pixel format not supported\n",
|
||||
|
|
@ -534,54 +534,54 @@ static void omap_disc_write(void *opaque, hwaddr addr,
|
|||
s->dispc.l[0].bpp = (value >> 1) & 0xf;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
|
||||
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
|
||||
s->dispc.l[0].tresh = value & 0x01ff01ff;
|
||||
break;
|
||||
case 0x0ac: /* DISPC_GFX_ROW_INC */
|
||||
case 0x0ac: /* DISPC_GFX_ROW_INC */
|
||||
s->dispc.l[0].rowinc = value;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
|
||||
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
|
||||
s->dispc.l[0].colinc = value;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
|
||||
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
|
||||
s->dispc.l[0].wininc = value;
|
||||
break;
|
||||
case 0x0b8: /* DISPC_GFX_TABLE_BA */
|
||||
case 0x0b8: /* DISPC_GFX_TABLE_BA */
|
||||
s->dispc.l[0].addr[2] = (hwaddr) value;
|
||||
s->dispc.invalidate = 1;
|
||||
break;
|
||||
|
||||
case 0x0bc: /* DISPC_VID1_BA0 */
|
||||
case 0x0c0: /* DISPC_VID1_BA1 */
|
||||
case 0x0c4: /* DISPC_VID1_POSITION */
|
||||
case 0x0c8: /* DISPC_VID1_SIZE */
|
||||
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
|
||||
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
|
||||
case 0x0d8: /* DISPC_VID1_ROW_INC */
|
||||
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
|
||||
case 0x0e0: /* DISPC_VID1_FIR */
|
||||
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
|
||||
case 0x0e8: /* DISPC_VID1_ACCU0 */
|
||||
case 0x0ec: /* DISPC_VID1_ACCU1 */
|
||||
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
|
||||
case 0x14c: /* DISPC_VID2_BA0 */
|
||||
case 0x150: /* DISPC_VID2_BA1 */
|
||||
case 0x154: /* DISPC_VID2_POSITION */
|
||||
case 0x158: /* DISPC_VID2_SIZE */
|
||||
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
|
||||
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
|
||||
case 0x168: /* DISPC_VID2_ROW_INC */
|
||||
case 0x16c: /* DISPC_VID2_PIXEL_INC */
|
||||
case 0x170: /* DISPC_VID2_FIR */
|
||||
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
|
||||
case 0x178: /* DISPC_VID2_ACCU0 */
|
||||
case 0x17c: /* DISPC_VID2_ACCU1 */
|
||||
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
|
||||
case 0x1d4: /* DISPC_DATA_CYCLE1 */
|
||||
case 0x1d8: /* DISPC_DATA_CYCLE2 */
|
||||
case 0x1dc: /* DISPC_DATA_CYCLE3 */
|
||||
case 0x0bc: /* DISPC_VID1_BA0 */
|
||||
case 0x0c0: /* DISPC_VID1_BA1 */
|
||||
case 0x0c4: /* DISPC_VID1_POSITION */
|
||||
case 0x0c8: /* DISPC_VID1_SIZE */
|
||||
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
|
||||
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
|
||||
case 0x0d8: /* DISPC_VID1_ROW_INC */
|
||||
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
|
||||
case 0x0e0: /* DISPC_VID1_FIR */
|
||||
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
|
||||
case 0x0e8: /* DISPC_VID1_ACCU0 */
|
||||
case 0x0ec: /* DISPC_VID1_ACCU1 */
|
||||
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
|
||||
case 0x14c: /* DISPC_VID2_BA0 */
|
||||
case 0x150: /* DISPC_VID2_BA1 */
|
||||
case 0x154: /* DISPC_VID2_POSITION */
|
||||
case 0x158: /* DISPC_VID2_SIZE */
|
||||
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
|
||||
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
|
||||
case 0x168: /* DISPC_VID2_ROW_INC */
|
||||
case 0x16c: /* DISPC_VID2_PIXEL_INC */
|
||||
case 0x170: /* DISPC_VID2_FIR */
|
||||
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
|
||||
case 0x178: /* DISPC_VID2_ACCU0 */
|
||||
case 0x17c: /* DISPC_VID2_ACCU1 */
|
||||
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
|
||||
case 0x1d4: /* DISPC_DATA_CYCLE1 */
|
||||
case 0x1d8: /* DISPC_DATA_CYCLE2 */
|
||||
case 0x1dc: /* DISPC_DATA_CYCLE3 */
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -617,14 +617,14 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
|
|||
if (!s->rfbi.enable || s->rfbi.busy)
|
||||
return;
|
||||
|
||||
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
|
||||
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
|
||||
/* TODO: in non-Bypass mode we probably need to just assert the
|
||||
* DRQ and wait for DMA to write the pixels. */
|
||||
qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
|
||||
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
|
||||
return;
|
||||
/* TODO: check that LCD output is enabled in DISPC. */
|
||||
|
||||
|
|
@ -665,7 +665,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
|
|||
omap_rfbi_transfer_stop(s);
|
||||
|
||||
/* TODO */
|
||||
s->dispc.irqst |= 1; /* FRAMEDONE */
|
||||
s->dispc.irqst |= 1; /* FRAMEDONE */
|
||||
omap_dispc_interrupt_update(s);
|
||||
}
|
||||
|
||||
|
|
@ -679,57 +679,57 @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* RFBI_REVISION */
|
||||
case 0x00: /* RFBI_REVISION */
|
||||
return 0x10;
|
||||
|
||||
case 0x10: /* RFBI_SYSCONFIG */
|
||||
case 0x10: /* RFBI_SYSCONFIG */
|
||||
return s->rfbi.idlemode;
|
||||
|
||||
case 0x14: /* RFBI_SYSSTATUS */
|
||||
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
|
||||
case 0x14: /* RFBI_SYSSTATUS */
|
||||
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
|
||||
|
||||
case 0x40: /* RFBI_CONTROL */
|
||||
case 0x40: /* RFBI_CONTROL */
|
||||
return s->rfbi.control;
|
||||
|
||||
case 0x44: /* RFBI_PIXELCNT */
|
||||
case 0x44: /* RFBI_PIXELCNT */
|
||||
return s->rfbi.pixels;
|
||||
|
||||
case 0x48: /* RFBI_LINE_NUMBER */
|
||||
case 0x48: /* RFBI_LINE_NUMBER */
|
||||
return s->rfbi.skiplines;
|
||||
|
||||
case 0x58: /* RFBI_READ */
|
||||
case 0x5c: /* RFBI_STATUS */
|
||||
case 0x58: /* RFBI_READ */
|
||||
case 0x5c: /* RFBI_STATUS */
|
||||
return s->rfbi.rxbuf;
|
||||
|
||||
case 0x60: /* RFBI_CONFIG0 */
|
||||
case 0x60: /* RFBI_CONFIG0 */
|
||||
return s->rfbi.config[0];
|
||||
case 0x64: /* RFBI_ONOFF_TIME0 */
|
||||
case 0x64: /* RFBI_ONOFF_TIME0 */
|
||||
return s->rfbi.time[0];
|
||||
case 0x68: /* RFBI_CYCLE_TIME0 */
|
||||
case 0x68: /* RFBI_CYCLE_TIME0 */
|
||||
return s->rfbi.time[1];
|
||||
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
|
||||
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
|
||||
return s->rfbi.data[0];
|
||||
case 0x70: /* RFBI_DATA_CYCLE2_0 */
|
||||
case 0x70: /* RFBI_DATA_CYCLE2_0 */
|
||||
return s->rfbi.data[1];
|
||||
case 0x74: /* RFBI_DATA_CYCLE3_0 */
|
||||
case 0x74: /* RFBI_DATA_CYCLE3_0 */
|
||||
return s->rfbi.data[2];
|
||||
|
||||
case 0x78: /* RFBI_CONFIG1 */
|
||||
case 0x78: /* RFBI_CONFIG1 */
|
||||
return s->rfbi.config[1];
|
||||
case 0x7c: /* RFBI_ONOFF_TIME1 */
|
||||
case 0x7c: /* RFBI_ONOFF_TIME1 */
|
||||
return s->rfbi.time[2];
|
||||
case 0x80: /* RFBI_CYCLE_TIME1 */
|
||||
case 0x80: /* RFBI_CYCLE_TIME1 */
|
||||
return s->rfbi.time[3];
|
||||
case 0x84: /* RFBI_DATA_CYCLE1_1 */
|
||||
case 0x84: /* RFBI_DATA_CYCLE1_1 */
|
||||
return s->rfbi.data[3];
|
||||
case 0x88: /* RFBI_DATA_CYCLE2_1 */
|
||||
case 0x88: /* RFBI_DATA_CYCLE2_1 */
|
||||
return s->rfbi.data[4];
|
||||
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
|
||||
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
|
||||
return s->rfbi.data[5];
|
||||
|
||||
case 0x90: /* RFBI_VSYNC_WIDTH */
|
||||
case 0x90: /* RFBI_VSYNC_WIDTH */
|
||||
return s->rfbi.vsync;
|
||||
case 0x94: /* RFBI_HSYNC_WIDTH */
|
||||
case 0x94: /* RFBI_HSYNC_WIDTH */
|
||||
return s->rfbi.hsync;
|
||||
}
|
||||
OMAP_BAD_REG(addr);
|
||||
|
|
@ -747,41 +747,41 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x10: /* RFBI_SYSCONFIG */
|
||||
if (value & 2) /* SOFTRESET */
|
||||
case 0x10: /* RFBI_SYSCONFIG */
|
||||
if (value & 2) /* SOFTRESET */
|
||||
omap_rfbi_reset(s);
|
||||
s->rfbi.idlemode = value & 0x19;
|
||||
break;
|
||||
|
||||
case 0x40: /* RFBI_CONTROL */
|
||||
case 0x40: /* RFBI_CONTROL */
|
||||
s->rfbi.control = value & 0xf;
|
||||
s->rfbi.enable = value & 1;
|
||||
if (value & (1 << 4) && /* ITE */
|
||||
if (value & (1 << 4) && /* ITE */
|
||||
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc))
|
||||
omap_rfbi_transfer_start(s);
|
||||
break;
|
||||
|
||||
case 0x44: /* RFBI_PIXELCNT */
|
||||
case 0x44: /* RFBI_PIXELCNT */
|
||||
s->rfbi.pixels = value;
|
||||
break;
|
||||
|
||||
case 0x48: /* RFBI_LINE_NUMBER */
|
||||
case 0x48: /* RFBI_LINE_NUMBER */
|
||||
s->rfbi.skiplines = value & 0x7ff;
|
||||
break;
|
||||
|
||||
case 0x4c: /* RFBI_CMD */
|
||||
case 0x4c: /* RFBI_CMD */
|
||||
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
|
||||
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
|
||||
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
|
||||
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
|
||||
break;
|
||||
case 0x50: /* RFBI_PARAM */
|
||||
case 0x50: /* RFBI_PARAM */
|
||||
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
|
||||
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
|
||||
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
|
||||
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
|
||||
break;
|
||||
case 0x54: /* RFBI_DATA */
|
||||
case 0x54: /* RFBI_DATA */
|
||||
/* TODO: take into account the format set up in s->rfbi.config[?] and
|
||||
* s->rfbi.data[?], but special-case the most usual scenario so that
|
||||
* speed doesn't suffer. */
|
||||
|
|
@ -796,7 +796,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
|
|||
if (!-- s->rfbi.pixels)
|
||||
omap_rfbi_transfer_stop(s);
|
||||
break;
|
||||
case 0x58: /* RFBI_READ */
|
||||
case 0x58: /* RFBI_READ */
|
||||
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
|
||||
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
|
||||
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
|
||||
|
|
@ -805,7 +805,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
|
|||
omap_rfbi_transfer_stop(s);
|
||||
break;
|
||||
|
||||
case 0x5c: /* RFBI_STATUS */
|
||||
case 0x5c: /* RFBI_STATUS */
|
||||
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
|
||||
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
|
||||
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
|
||||
|
|
@ -814,49 +814,49 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
|
|||
omap_rfbi_transfer_stop(s);
|
||||
break;
|
||||
|
||||
case 0x60: /* RFBI_CONFIG0 */
|
||||
case 0x60: /* RFBI_CONFIG0 */
|
||||
s->rfbi.config[0] = value & 0x003f1fff;
|
||||
break;
|
||||
|
||||
case 0x64: /* RFBI_ONOFF_TIME0 */
|
||||
case 0x64: /* RFBI_ONOFF_TIME0 */
|
||||
s->rfbi.time[0] = value & 0x3fffffff;
|
||||
break;
|
||||
case 0x68: /* RFBI_CYCLE_TIME0 */
|
||||
case 0x68: /* RFBI_CYCLE_TIME0 */
|
||||
s->rfbi.time[1] = value & 0x0fffffff;
|
||||
break;
|
||||
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
|
||||
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
|
||||
s->rfbi.data[0] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
case 0x70: /* RFBI_DATA_CYCLE2_0 */
|
||||
case 0x70: /* RFBI_DATA_CYCLE2_0 */
|
||||
s->rfbi.data[1] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
case 0x74: /* RFBI_DATA_CYCLE3_0 */
|
||||
case 0x74: /* RFBI_DATA_CYCLE3_0 */
|
||||
s->rfbi.data[2] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
case 0x78: /* RFBI_CONFIG1 */
|
||||
case 0x78: /* RFBI_CONFIG1 */
|
||||
s->rfbi.config[1] = value & 0x003f1fff;
|
||||
break;
|
||||
|
||||
case 0x7c: /* RFBI_ONOFF_TIME1 */
|
||||
case 0x7c: /* RFBI_ONOFF_TIME1 */
|
||||
s->rfbi.time[2] = value & 0x3fffffff;
|
||||
break;
|
||||
case 0x80: /* RFBI_CYCLE_TIME1 */
|
||||
case 0x80: /* RFBI_CYCLE_TIME1 */
|
||||
s->rfbi.time[3] = value & 0x0fffffff;
|
||||
break;
|
||||
case 0x84: /* RFBI_DATA_CYCLE1_1 */
|
||||
case 0x84: /* RFBI_DATA_CYCLE1_1 */
|
||||
s->rfbi.data[3] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
case 0x88: /* RFBI_DATA_CYCLE2_1 */
|
||||
case 0x88: /* RFBI_DATA_CYCLE2_1 */
|
||||
s->rfbi.data[4] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
|
||||
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
|
||||
s->rfbi.data[5] = value & 0x0f1f0f1f;
|
||||
break;
|
||||
|
||||
case 0x90: /* RFBI_VSYNC_WIDTH */
|
||||
case 0x90: /* RFBI_VSYNC_WIDTH */
|
||||
s->rfbi.vsync = value & 0xffff;
|
||||
break;
|
||||
case 0x94: /* RFBI_HSYNC_WIDTH */
|
||||
case 0x94: /* RFBI_HSYNC_WIDTH */
|
||||
s->rfbi.hsync = value & 0xffff;
|
||||
break;
|
||||
|
||||
|
|
@ -879,49 +879,49 @@ static uint64_t omap_venc_read(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* REV_ID */
|
||||
case 0x04: /* STATUS */
|
||||
case 0x08: /* F_CONTROL */
|
||||
case 0x10: /* VIDOUT_CTRL */
|
||||
case 0x14: /* SYNC_CTRL */
|
||||
case 0x1c: /* LLEN */
|
||||
case 0x20: /* FLENS */
|
||||
case 0x24: /* HFLTR_CTRL */
|
||||
case 0x28: /* CC_CARR_WSS_CARR */
|
||||
case 0x2c: /* C_PHASE */
|
||||
case 0x30: /* GAIN_U */
|
||||
case 0x34: /* GAIN_V */
|
||||
case 0x38: /* GAIN_Y */
|
||||
case 0x3c: /* BLACK_LEVEL */
|
||||
case 0x40: /* BLANK_LEVEL */
|
||||
case 0x44: /* X_COLOR */
|
||||
case 0x48: /* M_CONTROL */
|
||||
case 0x4c: /* BSTAMP_WSS_DATA */
|
||||
case 0x50: /* S_CARR */
|
||||
case 0x54: /* LINE21 */
|
||||
case 0x58: /* LN_SEL */
|
||||
case 0x5c: /* L21__WC_CTL */
|
||||
case 0x60: /* HTRIGGER_VTRIGGER */
|
||||
case 0x64: /* SAVID__EAVID */
|
||||
case 0x68: /* FLEN__FAL */
|
||||
case 0x6c: /* LAL__PHASE_RESET */
|
||||
case 0x70: /* HS_INT_START_STOP_X */
|
||||
case 0x74: /* HS_EXT_START_STOP_X */
|
||||
case 0x78: /* VS_INT_START_X */
|
||||
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
|
||||
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
|
||||
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
|
||||
case 0x88: /* VS_EXT_STOP_Y */
|
||||
case 0x90: /* AVID_START_STOP_X */
|
||||
case 0x94: /* AVID_START_STOP_Y */
|
||||
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
|
||||
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
|
||||
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
|
||||
case 0xb0: /* TVDETGP_INT_START_STOP_X */
|
||||
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
|
||||
case 0xb8: /* GEN_CTRL */
|
||||
case 0xc4: /* DAC_TST__DAC_A */
|
||||
case 0xc8: /* DAC_B__DAC_C */
|
||||
case 0x00: /* REV_ID */
|
||||
case 0x04: /* STATUS */
|
||||
case 0x08: /* F_CONTROL */
|
||||
case 0x10: /* VIDOUT_CTRL */
|
||||
case 0x14: /* SYNC_CTRL */
|
||||
case 0x1c: /* LLEN */
|
||||
case 0x20: /* FLENS */
|
||||
case 0x24: /* HFLTR_CTRL */
|
||||
case 0x28: /* CC_CARR_WSS_CARR */
|
||||
case 0x2c: /* C_PHASE */
|
||||
case 0x30: /* GAIN_U */
|
||||
case 0x34: /* GAIN_V */
|
||||
case 0x38: /* GAIN_Y */
|
||||
case 0x3c: /* BLACK_LEVEL */
|
||||
case 0x40: /* BLANK_LEVEL */
|
||||
case 0x44: /* X_COLOR */
|
||||
case 0x48: /* M_CONTROL */
|
||||
case 0x4c: /* BSTAMP_WSS_DATA */
|
||||
case 0x50: /* S_CARR */
|
||||
case 0x54: /* LINE21 */
|
||||
case 0x58: /* LN_SEL */
|
||||
case 0x5c: /* L21__WC_CTL */
|
||||
case 0x60: /* HTRIGGER_VTRIGGER */
|
||||
case 0x64: /* SAVID__EAVID */
|
||||
case 0x68: /* FLEN__FAL */
|
||||
case 0x6c: /* LAL__PHASE_RESET */
|
||||
case 0x70: /* HS_INT_START_STOP_X */
|
||||
case 0x74: /* HS_EXT_START_STOP_X */
|
||||
case 0x78: /* VS_INT_START_X */
|
||||
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
|
||||
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
|
||||
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
|
||||
case 0x88: /* VS_EXT_STOP_Y */
|
||||
case 0x90: /* AVID_START_STOP_X */
|
||||
case 0x94: /* AVID_START_STOP_Y */
|
||||
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
|
||||
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
|
||||
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
|
||||
case 0xb0: /* TVDETGP_INT_START_STOP_X */
|
||||
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
|
||||
case 0xb8: /* GEN_CTRL */
|
||||
case 0xc4: /* DAC_TST__DAC_A */
|
||||
case 0xc8: /* DAC_B__DAC_C */
|
||||
return 0;
|
||||
|
||||
default:
|
||||
|
|
@ -940,47 +940,47 @@ static void omap_venc_write(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x08: /* F_CONTROL */
|
||||
case 0x10: /* VIDOUT_CTRL */
|
||||
case 0x14: /* SYNC_CTRL */
|
||||
case 0x1c: /* LLEN */
|
||||
case 0x20: /* FLENS */
|
||||
case 0x24: /* HFLTR_CTRL */
|
||||
case 0x28: /* CC_CARR_WSS_CARR */
|
||||
case 0x2c: /* C_PHASE */
|
||||
case 0x30: /* GAIN_U */
|
||||
case 0x34: /* GAIN_V */
|
||||
case 0x38: /* GAIN_Y */
|
||||
case 0x3c: /* BLACK_LEVEL */
|
||||
case 0x40: /* BLANK_LEVEL */
|
||||
case 0x44: /* X_COLOR */
|
||||
case 0x48: /* M_CONTROL */
|
||||
case 0x4c: /* BSTAMP_WSS_DATA */
|
||||
case 0x50: /* S_CARR */
|
||||
case 0x54: /* LINE21 */
|
||||
case 0x58: /* LN_SEL */
|
||||
case 0x5c: /* L21__WC_CTL */
|
||||
case 0x60: /* HTRIGGER_VTRIGGER */
|
||||
case 0x64: /* SAVID__EAVID */
|
||||
case 0x68: /* FLEN__FAL */
|
||||
case 0x6c: /* LAL__PHASE_RESET */
|
||||
case 0x70: /* HS_INT_START_STOP_X */
|
||||
case 0x74: /* HS_EXT_START_STOP_X */
|
||||
case 0x78: /* VS_INT_START_X */
|
||||
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
|
||||
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
|
||||
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
|
||||
case 0x88: /* VS_EXT_STOP_Y */
|
||||
case 0x90: /* AVID_START_STOP_X */
|
||||
case 0x94: /* AVID_START_STOP_Y */
|
||||
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
|
||||
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
|
||||
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
|
||||
case 0xb0: /* TVDETGP_INT_START_STOP_X */
|
||||
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
|
||||
case 0xb8: /* GEN_CTRL */
|
||||
case 0xc4: /* DAC_TST__DAC_A */
|
||||
case 0xc8: /* DAC_B__DAC_C */
|
||||
case 0x08: /* F_CONTROL */
|
||||
case 0x10: /* VIDOUT_CTRL */
|
||||
case 0x14: /* SYNC_CTRL */
|
||||
case 0x1c: /* LLEN */
|
||||
case 0x20: /* FLENS */
|
||||
case 0x24: /* HFLTR_CTRL */
|
||||
case 0x28: /* CC_CARR_WSS_CARR */
|
||||
case 0x2c: /* C_PHASE */
|
||||
case 0x30: /* GAIN_U */
|
||||
case 0x34: /* GAIN_V */
|
||||
case 0x38: /* GAIN_Y */
|
||||
case 0x3c: /* BLACK_LEVEL */
|
||||
case 0x40: /* BLANK_LEVEL */
|
||||
case 0x44: /* X_COLOR */
|
||||
case 0x48: /* M_CONTROL */
|
||||
case 0x4c: /* BSTAMP_WSS_DATA */
|
||||
case 0x50: /* S_CARR */
|
||||
case 0x54: /* LINE21 */
|
||||
case 0x58: /* LN_SEL */
|
||||
case 0x5c: /* L21__WC_CTL */
|
||||
case 0x60: /* HTRIGGER_VTRIGGER */
|
||||
case 0x64: /* SAVID__EAVID */
|
||||
case 0x68: /* FLEN__FAL */
|
||||
case 0x6c: /* LAL__PHASE_RESET */
|
||||
case 0x70: /* HS_INT_START_STOP_X */
|
||||
case 0x74: /* HS_EXT_START_STOP_X */
|
||||
case 0x78: /* VS_INT_START_X */
|
||||
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
|
||||
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
|
||||
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
|
||||
case 0x88: /* VS_EXT_STOP_Y */
|
||||
case 0x90: /* AVID_START_STOP_X */
|
||||
case 0x94: /* AVID_START_STOP_Y */
|
||||
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
|
||||
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
|
||||
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
|
||||
case 0xb0: /* TVDETGP_INT_START_STOP_X */
|
||||
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
|
||||
case 0xb8: /* GEN_CTRL */
|
||||
case 0xc4: /* DAC_TST__DAC_A */
|
||||
case 0xc8: /* DAC_B__DAC_C */
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -1002,15 +1002,15 @@ static uint64_t omap_im3_read(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x0a8: /* SBIMERRLOGA */
|
||||
case 0x0b0: /* SBIMERRLOG */
|
||||
case 0x190: /* SBIMSTATE */
|
||||
case 0x198: /* SBTMSTATE_L */
|
||||
case 0x19c: /* SBTMSTATE_H */
|
||||
case 0x1a8: /* SBIMCONFIG_L */
|
||||
case 0x1ac: /* SBIMCONFIG_H */
|
||||
case 0x1f8: /* SBID_L */
|
||||
case 0x1fc: /* SBID_H */
|
||||
case 0x0a8: /* SBIMERRLOGA */
|
||||
case 0x0b0: /* SBIMERRLOG */
|
||||
case 0x190: /* SBIMSTATE */
|
||||
case 0x198: /* SBTMSTATE_L */
|
||||
case 0x19c: /* SBTMSTATE_H */
|
||||
case 0x1a8: /* SBIMCONFIG_L */
|
||||
case 0x1ac: /* SBIMCONFIG_H */
|
||||
case 0x1f8: /* SBID_L */
|
||||
case 0x1fc: /* SBID_H */
|
||||
return 0;
|
||||
|
||||
default:
|
||||
|
|
@ -1029,12 +1029,12 @@ static void omap_im3_write(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x0b0: /* SBIMERRLOG */
|
||||
case 0x190: /* SBIMSTATE */
|
||||
case 0x198: /* SBTMSTATE_L */
|
||||
case 0x19c: /* SBTMSTATE_H */
|
||||
case 0x1a8: /* SBIMCONFIG_L */
|
||||
case 0x1ac: /* SBIMCONFIG_H */
|
||||
case 0x0b0: /* SBIMERRLOG */
|
||||
case 0x190: /* SBIMSTATE */
|
||||
case 0x198: /* SBTMSTATE_L */
|
||||
case 0x19c: /* SBTMSTATE_H */
|
||||
case 0x1a8: /* SBIMCONFIG_L */
|
||||
case 0x1ac: /* SBIMCONFIG_H */
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue