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hw/display: fix tab indentation
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <5cefd05b4d3721d416e48e6df19df18cb6338933.1666707782.git.amarjargal16@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Amarjargal Gundjalam
Thomas Huth
parent
ef99aa2a31
commit
a076a3dcbf
6 changed files with 1499 additions and 1499 deletions
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@ -123,14 +123,14 @@ typedef struct {
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/* Bytes(!) per pixel */
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static const int blizzard_iformat_bpp[0x10] = {
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0,
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2, /* RGB 5:6:5*/
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3, /* RGB 6:6:6 mode 1 */
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3, /* RGB 8:8:8 mode 1 */
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2, /* RGB 5:6:5*/
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3, /* RGB 6:6:6 mode 1 */
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3, /* RGB 8:8:8 mode 1 */
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0, 0,
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4, /* RGB 6:6:6 mode 2 */
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4, /* RGB 8:8:8 mode 2 */
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0, /* YUV 4:2:2 */
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0, /* YUV 4:2:0 */
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4, /* RGB 6:6:6 mode 2 */
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4, /* RGB 8:8:8 mode 2 */
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0, /* YUV 4:2:2 */
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0, /* YUV 4:2:0 */
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0, 0, 0, 0, 0, 0,
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};
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@ -281,196 +281,196 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
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BlizzardState *s = (BlizzardState *) opaque;
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switch (reg) {
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case 0x00: /* Revision Code */
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case 0x00: /* Revision Code */
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return 0xa5;
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case 0x02: /* Configuration Readback */
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return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
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case 0x02: /* Configuration Readback */
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return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
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case 0x04: /* PLL M-Divider */
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case 0x04: /* PLL M-Divider */
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return (s->pll - 1) | (1 << 7);
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case 0x06: /* PLL Lock Range Control */
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case 0x06: /* PLL Lock Range Control */
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return s->pll_range;
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case 0x08: /* PLL Lock Synthesis Control 0 */
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case 0x08: /* PLL Lock Synthesis Control 0 */
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return s->pll_ctrl & 0xff;
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case 0x0a: /* PLL Lock Synthesis Control 1 */
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case 0x0a: /* PLL Lock Synthesis Control 1 */
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return s->pll_ctrl >> 8;
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case 0x0c: /* PLL Mode Control 0 */
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case 0x0c: /* PLL Mode Control 0 */
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return s->pll_mode;
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case 0x0e: /* Clock-Source Select */
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case 0x0e: /* Clock-Source Select */
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return s->clksel;
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case 0x10: /* Memory Controller Activate */
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case 0x14: /* Memory Controller Bank 0 Status Flag */
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case 0x10: /* Memory Controller Activate */
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case 0x14: /* Memory Controller Bank 0 Status Flag */
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return s->memenable;
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case 0x18: /* Auto-Refresh Interval Setting 0 */
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case 0x18: /* Auto-Refresh Interval Setting 0 */
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return s->memrefresh & 0xff;
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case 0x1a: /* Auto-Refresh Interval Setting 1 */
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case 0x1a: /* Auto-Refresh Interval Setting 1 */
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return s->memrefresh >> 8;
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case 0x1c: /* Power-On Sequence Timing Control */
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case 0x1c: /* Power-On Sequence Timing Control */
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return s->timing[0];
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case 0x1e: /* Timing Control 0 */
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case 0x1e: /* Timing Control 0 */
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return s->timing[1];
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case 0x20: /* Timing Control 1 */
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case 0x20: /* Timing Control 1 */
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return s->timing[2];
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case 0x24: /* Arbitration Priority Control */
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case 0x24: /* Arbitration Priority Control */
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return s->priority;
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case 0x28: /* LCD Panel Configuration */
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case 0x28: /* LCD Panel Configuration */
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return s->lcd_config;
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case 0x2a: /* LCD Horizontal Display Width */
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case 0x2a: /* LCD Horizontal Display Width */
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return s->x >> 3;
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case 0x2c: /* LCD Horizontal Non-display Period */
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case 0x2c: /* LCD Horizontal Non-display Period */
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return s->hndp;
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case 0x2e: /* LCD Vertical Display Height 0 */
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case 0x2e: /* LCD Vertical Display Height 0 */
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return s->y & 0xff;
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case 0x30: /* LCD Vertical Display Height 1 */
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case 0x30: /* LCD Vertical Display Height 1 */
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return s->y >> 8;
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case 0x32: /* LCD Vertical Non-display Period */
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case 0x32: /* LCD Vertical Non-display Period */
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return s->vndp;
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case 0x34: /* LCD HS Pulse-width */
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case 0x34: /* LCD HS Pulse-width */
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return s->hsync;
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case 0x36: /* LCd HS Pulse Start Position */
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case 0x36: /* LCd HS Pulse Start Position */
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return s->skipx >> 3;
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case 0x38: /* LCD VS Pulse-width */
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case 0x38: /* LCD VS Pulse-width */
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return s->vsync;
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case 0x3a: /* LCD VS Pulse Start Position */
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case 0x3a: /* LCD VS Pulse Start Position */
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return s->skipy;
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case 0x3c: /* PCLK Polarity */
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case 0x3c: /* PCLK Polarity */
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return s->pclk;
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case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
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case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
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return s->hssi_config[0];
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case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
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case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
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return s->hssi_config[1];
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case 0x42: /* High-speed Serial Interface Tx Mode */
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case 0x42: /* High-speed Serial Interface Tx Mode */
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return s->hssi_config[2];
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case 0x44: /* TV Display Configuration */
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case 0x44: /* TV Display Configuration */
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return s->tv_config;
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case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
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case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
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return s->tv_timing[(reg - 0x46) >> 1];
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case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
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case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
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return s->vbi;
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case 0x50: /* TV Horizontal Start Position */
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case 0x50: /* TV Horizontal Start Position */
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return s->tv_x;
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case 0x52: /* TV Vertical Start Position */
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case 0x52: /* TV Vertical Start Position */
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return s->tv_y;
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case 0x54: /* TV Test Pattern Setting */
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case 0x54: /* TV Test Pattern Setting */
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return s->tv_test;
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case 0x56: /* TV Filter Setting */
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case 0x56: /* TV Filter Setting */
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return s->tv_filter_config;
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case 0x58: /* TV Filter Coefficient Index */
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case 0x58: /* TV Filter Coefficient Index */
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return s->tv_filter_idx;
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case 0x5a: /* TV Filter Coefficient Data */
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case 0x5a: /* TV Filter Coefficient Data */
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if (s->tv_filter_idx < 0x20)
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return s->tv_filter_coeff[s->tv_filter_idx ++];
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return 0;
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case 0x60: /* Input YUV/RGB Translate Mode 0 */
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case 0x60: /* Input YUV/RGB Translate Mode 0 */
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return s->yrc[0];
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case 0x62: /* Input YUV/RGB Translate Mode 1 */
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case 0x62: /* Input YUV/RGB Translate Mode 1 */
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return s->yrc[1];
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case 0x64: /* U Data Fix */
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case 0x64: /* U Data Fix */
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return s->u;
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case 0x66: /* V Data Fix */
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case 0x66: /* V Data Fix */
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return s->v;
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case 0x68: /* Display Mode */
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case 0x68: /* Display Mode */
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return s->mode;
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case 0x6a: /* Special Effects */
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case 0x6a: /* Special Effects */
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return s->effect;
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case 0x6c: /* Input Window X Start Position 0 */
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case 0x6c: /* Input Window X Start Position 0 */
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return s->ix[0] & 0xff;
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case 0x6e: /* Input Window X Start Position 1 */
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case 0x6e: /* Input Window X Start Position 1 */
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return s->ix[0] >> 3;
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case 0x70: /* Input Window Y Start Position 0 */
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case 0x70: /* Input Window Y Start Position 0 */
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return s->ix[0] & 0xff;
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case 0x72: /* Input Window Y Start Position 1 */
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case 0x72: /* Input Window Y Start Position 1 */
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return s->ix[0] >> 3;
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case 0x74: /* Input Window X End Position 0 */
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case 0x74: /* Input Window X End Position 0 */
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return s->ix[1] & 0xff;
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case 0x76: /* Input Window X End Position 1 */
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case 0x76: /* Input Window X End Position 1 */
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return s->ix[1] >> 3;
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case 0x78: /* Input Window Y End Position 0 */
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case 0x78: /* Input Window Y End Position 0 */
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return s->ix[1] & 0xff;
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case 0x7a: /* Input Window Y End Position 1 */
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case 0x7a: /* Input Window Y End Position 1 */
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return s->ix[1] >> 3;
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case 0x7c: /* Output Window X Start Position 0 */
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case 0x7c: /* Output Window X Start Position 0 */
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return s->ox[0] & 0xff;
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case 0x7e: /* Output Window X Start Position 1 */
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case 0x7e: /* Output Window X Start Position 1 */
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return s->ox[0] >> 3;
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case 0x80: /* Output Window Y Start Position 0 */
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case 0x80: /* Output Window Y Start Position 0 */
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return s->oy[0] & 0xff;
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case 0x82: /* Output Window Y Start Position 1 */
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case 0x82: /* Output Window Y Start Position 1 */
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return s->oy[0] >> 3;
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case 0x84: /* Output Window X End Position 0 */
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case 0x84: /* Output Window X End Position 0 */
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return s->ox[1] & 0xff;
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case 0x86: /* Output Window X End Position 1 */
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case 0x86: /* Output Window X End Position 1 */
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return s->ox[1] >> 3;
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case 0x88: /* Output Window Y End Position 0 */
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case 0x88: /* Output Window Y End Position 0 */
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return s->oy[1] & 0xff;
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case 0x8a: /* Output Window Y End Position 1 */
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case 0x8a: /* Output Window Y End Position 1 */
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return s->oy[1] >> 3;
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case 0x8c: /* Input Data Format */
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case 0x8c: /* Input Data Format */
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return s->iformat;
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case 0x8e: /* Data Source Select */
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case 0x8e: /* Data Source Select */
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return s->source;
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case 0x90: /* Display Memory Data Port */
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case 0x90: /* Display Memory Data Port */
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return 0;
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case 0xa8: /* Border Color 0 */
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case 0xa8: /* Border Color 0 */
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return s->border_r;
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case 0xaa: /* Border Color 1 */
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case 0xaa: /* Border Color 1 */
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return s->border_g;
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case 0xac: /* Border Color 2 */
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case 0xac: /* Border Color 2 */
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return s->border_b;
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case 0xb4: /* Gamma Correction Enable */
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case 0xb4: /* Gamma Correction Enable */
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return s->gamma_config;
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case 0xb6: /* Gamma Correction Table Index */
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case 0xb6: /* Gamma Correction Table Index */
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return s->gamma_idx;
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case 0xb8: /* Gamma Correction Table Data */
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case 0xb8: /* Gamma Correction Table Data */
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return s->gamma_lut[s->gamma_idx ++];
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case 0xba: /* 3x3 Matrix Enable */
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case 0xba: /* 3x3 Matrix Enable */
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return s->matrix_ena;
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case 0xbc ... 0xde: /* Coefficient Registers */
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case 0xbc ... 0xde: /* Coefficient Registers */
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return s->matrix_coeff[(reg - 0xbc) >> 1];
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case 0xe0: /* 3x3 Matrix Red Offset */
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case 0xe0: /* 3x3 Matrix Red Offset */
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return s->matrix_r;
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case 0xe2: /* 3x3 Matrix Green Offset */
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case 0xe2: /* 3x3 Matrix Green Offset */
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return s->matrix_g;
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case 0xe4: /* 3x3 Matrix Blue Offset */
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case 0xe4: /* 3x3 Matrix Blue Offset */
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return s->matrix_b;
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case 0xe6: /* Power-save */
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case 0xe6: /* Power-save */
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return s->pm;
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case 0xe8: /* Non-display Period Control / Status */
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case 0xe8: /* Non-display Period Control / Status */
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return s->status | (1 << 5);
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case 0xea: /* RGB Interface Control */
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case 0xea: /* RGB Interface Control */
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return s->rgbgpio_dir;
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case 0xec: /* RGB Interface Status */
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case 0xec: /* RGB Interface Status */
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return s->rgbgpio;
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case 0xee: /* General-purpose IO Pins Configuration */
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case 0xee: /* General-purpose IO Pins Configuration */
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return s->gpio_dir;
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case 0xf0: /* General-purpose IO Pins Status / Control */
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case 0xf0: /* General-purpose IO Pins Status / Control */
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return s->gpio;
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case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
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case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
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return s->gpio_edge[0];
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case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
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case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
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return s->gpio_edge[1];
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case 0xf6: /* GPIO Interrupt Status */
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case 0xf6: /* GPIO Interrupt Status */
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return s->gpio_irq;
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case 0xf8: /* GPIO Pull-down Control */
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case 0xf8: /* GPIO Pull-down Control */
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return s->gpio_pdown;
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default:
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@ -484,157 +484,157 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
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BlizzardState *s = (BlizzardState *) opaque;
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switch (reg) {
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case 0x04: /* PLL M-Divider */
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case 0x04: /* PLL M-Divider */
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s->pll = (value & 0x3f) + 1;
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break;
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case 0x06: /* PLL Lock Range Control */
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case 0x06: /* PLL Lock Range Control */
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s->pll_range = value & 3;
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break;
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case 0x08: /* PLL Lock Synthesis Control 0 */
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case 0x08: /* PLL Lock Synthesis Control 0 */
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s->pll_ctrl &= 0xf00;
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s->pll_ctrl |= (value << 0) & 0x0ff;
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break;
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case 0x0a: /* PLL Lock Synthesis Control 1 */
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case 0x0a: /* PLL Lock Synthesis Control 1 */
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s->pll_ctrl &= 0x0ff;
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s->pll_ctrl |= (value << 8) & 0xf00;
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break;
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case 0x0c: /* PLL Mode Control 0 */
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case 0x0c: /* PLL Mode Control 0 */
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s->pll_mode = value & 0x77;
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if ((value & 3) == 0 || (value & 3) == 3)
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fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
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__func__, value & 3);
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break;
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case 0x0e: /* Clock-Source Select */
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case 0x0e: /* Clock-Source Select */
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s->clksel = value & 0xff;
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break;
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case 0x10: /* Memory Controller Activate */
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case 0x10: /* Memory Controller Activate */
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s->memenable = value & 1;
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break;
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case 0x14: /* Memory Controller Bank 0 Status Flag */
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case 0x14: /* Memory Controller Bank 0 Status Flag */
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break;
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case 0x18: /* Auto-Refresh Interval Setting 0 */
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case 0x18: /* Auto-Refresh Interval Setting 0 */
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s->memrefresh &= 0xf00;
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s->memrefresh |= (value << 0) & 0x0ff;
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break;
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case 0x1a: /* Auto-Refresh Interval Setting 1 */
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case 0x1a: /* Auto-Refresh Interval Setting 1 */
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s->memrefresh &= 0x0ff;
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s->memrefresh |= (value << 8) & 0xf00;
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break;
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case 0x1c: /* Power-On Sequence Timing Control */
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case 0x1c: /* Power-On Sequence Timing Control */
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s->timing[0] = value & 0x7f;
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break;
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case 0x1e: /* Timing Control 0 */
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case 0x1e: /* Timing Control 0 */
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s->timing[1] = value & 0x17;
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break;
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case 0x20: /* Timing Control 1 */
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case 0x20: /* Timing Control 1 */
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s->timing[2] = value & 0x35;
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break;
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case 0x24: /* Arbitration Priority Control */
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case 0x24: /* Arbitration Priority Control */
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s->priority = value & 1;
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break;
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case 0x28: /* LCD Panel Configuration */
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case 0x28: /* LCD Panel Configuration */
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s->lcd_config = value & 0xff;
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if (value & (1 << 7))
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fprintf(stderr, "%s: data swap not supported!\n", __func__);
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break;
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case 0x2a: /* LCD Horizontal Display Width */
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case 0x2a: /* LCD Horizontal Display Width */
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s->x = value << 3;
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break;
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case 0x2c: /* LCD Horizontal Non-display Period */
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case 0x2c: /* LCD Horizontal Non-display Period */
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s->hndp = value & 0xff;
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break;
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case 0x2e: /* LCD Vertical Display Height 0 */
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case 0x2e: /* LCD Vertical Display Height 0 */
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s->y &= 0x300;
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s->y |= (value << 0) & 0x0ff;
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break;
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case 0x30: /* LCD Vertical Display Height 1 */
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case 0x30: /* LCD Vertical Display Height 1 */
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s->y &= 0x0ff;
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s->y |= (value << 8) & 0x300;
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break;
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case 0x32: /* LCD Vertical Non-display Period */
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case 0x32: /* LCD Vertical Non-display Period */
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s->vndp = value & 0xff;
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break;
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case 0x34: /* LCD HS Pulse-width */
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case 0x34: /* LCD HS Pulse-width */
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s->hsync = value & 0xff;
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break;
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case 0x36: /* LCD HS Pulse Start Position */
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case 0x36: /* LCD HS Pulse Start Position */
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s->skipx = value & 0xff;
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break;
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case 0x38: /* LCD VS Pulse-width */
|
||||
case 0x38: /* LCD VS Pulse-width */
|
||||
s->vsync = value & 0xbf;
|
||||
break;
|
||||
case 0x3a: /* LCD VS Pulse Start Position */
|
||||
case 0x3a: /* LCD VS Pulse Start Position */
|
||||
s->skipy = value & 0xff;
|
||||
break;
|
||||
|
||||
case 0x3c: /* PCLK Polarity */
|
||||
case 0x3c: /* PCLK Polarity */
|
||||
s->pclk = value & 0x82;
|
||||
/* Affects calculation of s->hndp, s->hsync and s->skipx. */
|
||||
break;
|
||||
|
||||
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
|
||||
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
|
||||
s->hssi_config[0] = value;
|
||||
break;
|
||||
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
|
||||
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
|
||||
s->hssi_config[1] = value;
|
||||
if (((value >> 4) & 3) == 3)
|
||||
fprintf(stderr, "%s: Illegal active-data-links value\n",
|
||||
__func__);
|
||||
break;
|
||||
case 0x42: /* High-speed Serial Interface Tx Mode */
|
||||
case 0x42: /* High-speed Serial Interface Tx Mode */
|
||||
s->hssi_config[2] = value & 0xbd;
|
||||
break;
|
||||
|
||||
case 0x44: /* TV Display Configuration */
|
||||
case 0x44: /* TV Display Configuration */
|
||||
s->tv_config = value & 0xfe;
|
||||
break;
|
||||
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
|
||||
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
|
||||
s->tv_timing[(reg - 0x46) >> 1] = value;
|
||||
break;
|
||||
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
|
||||
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
|
||||
s->vbi = value;
|
||||
break;
|
||||
case 0x50: /* TV Horizontal Start Position */
|
||||
case 0x50: /* TV Horizontal Start Position */
|
||||
s->tv_x = value;
|
||||
break;
|
||||
case 0x52: /* TV Vertical Start Position */
|
||||
case 0x52: /* TV Vertical Start Position */
|
||||
s->tv_y = value & 0x7f;
|
||||
break;
|
||||
case 0x54: /* TV Test Pattern Setting */
|
||||
case 0x54: /* TV Test Pattern Setting */
|
||||
s->tv_test = value;
|
||||
break;
|
||||
case 0x56: /* TV Filter Setting */
|
||||
case 0x56: /* TV Filter Setting */
|
||||
s->tv_filter_config = value & 0xbf;
|
||||
break;
|
||||
case 0x58: /* TV Filter Coefficient Index */
|
||||
case 0x58: /* TV Filter Coefficient Index */
|
||||
s->tv_filter_idx = value & 0x1f;
|
||||
break;
|
||||
case 0x5a: /* TV Filter Coefficient Data */
|
||||
case 0x5a: /* TV Filter Coefficient Data */
|
||||
if (s->tv_filter_idx < 0x20)
|
||||
s->tv_filter_coeff[s->tv_filter_idx ++] = value;
|
||||
break;
|
||||
|
||||
case 0x60: /* Input YUV/RGB Translate Mode 0 */
|
||||
case 0x60: /* Input YUV/RGB Translate Mode 0 */
|
||||
s->yrc[0] = value & 0xb0;
|
||||
break;
|
||||
case 0x62: /* Input YUV/RGB Translate Mode 1 */
|
||||
case 0x62: /* Input YUV/RGB Translate Mode 1 */
|
||||
s->yrc[1] = value & 0x30;
|
||||
break;
|
||||
case 0x64: /* U Data Fix */
|
||||
case 0x64: /* U Data Fix */
|
||||
s->u = value & 0xff;
|
||||
break;
|
||||
case 0x66: /* V Data Fix */
|
||||
case 0x66: /* V Data Fix */
|
||||
s->v = value & 0xff;
|
||||
break;
|
||||
|
||||
case 0x68: /* Display Mode */
|
||||
case 0x68: /* Display Mode */
|
||||
if ((s->mode ^ value) & 3)
|
||||
s->invalidate = 1;
|
||||
s->mode = value & 0xb7;
|
||||
|
|
@ -644,83 +644,83 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
|
|||
fprintf(stderr, "%s: Macrovision enable attempt!\n", __func__);
|
||||
break;
|
||||
|
||||
case 0x6a: /* Special Effects */
|
||||
case 0x6a: /* Special Effects */
|
||||
s->effect = value & 0xfb;
|
||||
break;
|
||||
|
||||
case 0x6c: /* Input Window X Start Position 0 */
|
||||
case 0x6c: /* Input Window X Start Position 0 */
|
||||
s->ix[0] &= 0x300;
|
||||
s->ix[0] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x6e: /* Input Window X Start Position 1 */
|
||||
case 0x6e: /* Input Window X Start Position 1 */
|
||||
s->ix[0] &= 0x0ff;
|
||||
s->ix[0] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x70: /* Input Window Y Start Position 0 */
|
||||
case 0x70: /* Input Window Y Start Position 0 */
|
||||
s->iy[0] &= 0x300;
|
||||
s->iy[0] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x72: /* Input Window Y Start Position 1 */
|
||||
case 0x72: /* Input Window Y Start Position 1 */
|
||||
s->iy[0] &= 0x0ff;
|
||||
s->iy[0] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x74: /* Input Window X End Position 0 */
|
||||
case 0x74: /* Input Window X End Position 0 */
|
||||
s->ix[1] &= 0x300;
|
||||
s->ix[1] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x76: /* Input Window X End Position 1 */
|
||||
case 0x76: /* Input Window X End Position 1 */
|
||||
s->ix[1] &= 0x0ff;
|
||||
s->ix[1] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x78: /* Input Window Y End Position 0 */
|
||||
case 0x78: /* Input Window Y End Position 0 */
|
||||
s->iy[1] &= 0x300;
|
||||
s->iy[1] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x7a: /* Input Window Y End Position 1 */
|
||||
case 0x7a: /* Input Window Y End Position 1 */
|
||||
s->iy[1] &= 0x0ff;
|
||||
s->iy[1] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x7c: /* Output Window X Start Position 0 */
|
||||
case 0x7c: /* Output Window X Start Position 0 */
|
||||
s->ox[0] &= 0x300;
|
||||
s->ox[0] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x7e: /* Output Window X Start Position 1 */
|
||||
case 0x7e: /* Output Window X Start Position 1 */
|
||||
s->ox[0] &= 0x0ff;
|
||||
s->ox[0] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x80: /* Output Window Y Start Position 0 */
|
||||
case 0x80: /* Output Window Y Start Position 0 */
|
||||
s->oy[0] &= 0x300;
|
||||
s->oy[0] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x82: /* Output Window Y Start Position 1 */
|
||||
case 0x82: /* Output Window Y Start Position 1 */
|
||||
s->oy[0] &= 0x0ff;
|
||||
s->oy[0] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x84: /* Output Window X End Position 0 */
|
||||
case 0x84: /* Output Window X End Position 0 */
|
||||
s->ox[1] &= 0x300;
|
||||
s->ox[1] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x86: /* Output Window X End Position 1 */
|
||||
case 0x86: /* Output Window X End Position 1 */
|
||||
s->ox[1] &= 0x0ff;
|
||||
s->ox[1] |= (value << 8) & 0x300;
|
||||
break;
|
||||
case 0x88: /* Output Window Y End Position 0 */
|
||||
case 0x88: /* Output Window Y End Position 0 */
|
||||
s->oy[1] &= 0x300;
|
||||
s->oy[1] |= (value << 0) & 0x0ff;
|
||||
break;
|
||||
case 0x8a: /* Output Window Y End Position 1 */
|
||||
case 0x8a: /* Output Window Y End Position 1 */
|
||||
s->oy[1] &= 0x0ff;
|
||||
s->oy[1] |= (value << 8) & 0x300;
|
||||
break;
|
||||
|
||||
case 0x8c: /* Input Data Format */
|
||||
case 0x8c: /* Input Data Format */
|
||||
s->iformat = value & 0xf;
|
||||
s->bpp = blizzard_iformat_bpp[s->iformat];
|
||||
if (!s->bpp)
|
||||
fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
|
||||
__func__, s->iformat);
|
||||
break;
|
||||
case 0x8e: /* Data Source Select */
|
||||
case 0x8e: /* Data Source Select */
|
||||
s->source = value & 7;
|
||||
/* Currently all windows will be "destructive overlays". */
|
||||
if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
|
||||
|
|
@ -735,7 +735,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
|
|||
blizzard_transfer_setup(s);
|
||||
break;
|
||||
|
||||
case 0x90: /* Display Memory Data Port */
|
||||
case 0x90: /* Display Memory Data Port */
|
||||
if (!s->data.len && !blizzard_transfer_setup(s))
|
||||
break;
|
||||
|
||||
|
|
@ -744,73 +744,73 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
|
|||
blizzard_window(s);
|
||||
break;
|
||||
|
||||
case 0xa8: /* Border Color 0 */
|
||||
case 0xa8: /* Border Color 0 */
|
||||
s->border_r = value;
|
||||
break;
|
||||
case 0xaa: /* Border Color 1 */
|
||||
case 0xaa: /* Border Color 1 */
|
||||
s->border_g = value;
|
||||
break;
|
||||
case 0xac: /* Border Color 2 */
|
||||
case 0xac: /* Border Color 2 */
|
||||
s->border_b = value;
|
||||
break;
|
||||
|
||||
case 0xb4: /* Gamma Correction Enable */
|
||||
case 0xb4: /* Gamma Correction Enable */
|
||||
s->gamma_config = value & 0x87;
|
||||
break;
|
||||
case 0xb6: /* Gamma Correction Table Index */
|
||||
case 0xb6: /* Gamma Correction Table Index */
|
||||
s->gamma_idx = value;
|
||||
break;
|
||||
case 0xb8: /* Gamma Correction Table Data */
|
||||
case 0xb8: /* Gamma Correction Table Data */
|
||||
s->gamma_lut[s->gamma_idx ++] = value;
|
||||
break;
|
||||
|
||||
case 0xba: /* 3x3 Matrix Enable */
|
||||
case 0xba: /* 3x3 Matrix Enable */
|
||||
s->matrix_ena = value & 1;
|
||||
break;
|
||||
case 0xbc ... 0xde: /* Coefficient Registers */
|
||||
case 0xbc ... 0xde: /* Coefficient Registers */
|
||||
s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
|
||||
break;
|
||||
case 0xe0: /* 3x3 Matrix Red Offset */
|
||||
case 0xe0: /* 3x3 Matrix Red Offset */
|
||||
s->matrix_r = value;
|
||||
break;
|
||||
case 0xe2: /* 3x3 Matrix Green Offset */
|
||||
case 0xe2: /* 3x3 Matrix Green Offset */
|
||||
s->matrix_g = value;
|
||||
break;
|
||||
case 0xe4: /* 3x3 Matrix Blue Offset */
|
||||
case 0xe4: /* 3x3 Matrix Blue Offset */
|
||||
s->matrix_b = value;
|
||||
break;
|
||||
|
||||
case 0xe6: /* Power-save */
|
||||
case 0xe6: /* Power-save */
|
||||
s->pm = value & 0x83;
|
||||
if (value & s->mode & 1)
|
||||
fprintf(stderr, "%s: The display must be disabled before entering "
|
||||
"Standby Mode\n", __func__);
|
||||
break;
|
||||
case 0xe8: /* Non-display Period Control / Status */
|
||||
case 0xe8: /* Non-display Period Control / Status */
|
||||
s->status = value & 0x1b;
|
||||
break;
|
||||
case 0xea: /* RGB Interface Control */
|
||||
case 0xea: /* RGB Interface Control */
|
||||
s->rgbgpio_dir = value & 0x8f;
|
||||
break;
|
||||
case 0xec: /* RGB Interface Status */
|
||||
case 0xec: /* RGB Interface Status */
|
||||
s->rgbgpio = value & 0xcf;
|
||||
break;
|
||||
case 0xee: /* General-purpose IO Pins Configuration */
|
||||
case 0xee: /* General-purpose IO Pins Configuration */
|
||||
s->gpio_dir = value;
|
||||
break;
|
||||
case 0xf0: /* General-purpose IO Pins Status / Control */
|
||||
case 0xf0: /* General-purpose IO Pins Status / Control */
|
||||
s->gpio = value;
|
||||
break;
|
||||
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
|
||||
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
|
||||
s->gpio_edge[0] = value;
|
||||
break;
|
||||
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
|
||||
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
|
||||
s->gpio_edge[1] = value;
|
||||
break;
|
||||
case 0xf6: /* GPIO Interrupt Status */
|
||||
case 0xf6: /* GPIO Interrupt Status */
|
||||
s->gpio_irq &= value;
|
||||
break;
|
||||
case 0xf8: /* GPIO Pull-down Control */
|
||||
case 0xf8: /* GPIO Pull-down Control */
|
||||
s->gpio_pdown = value;
|
||||
break;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue