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target/arm: Convert aes and sm4 to gvec helpers

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With this conversion, we will be able to use the same helpers
with sve.  In particular, pass 3 vector parameters for the
3-operand operations; for advsimd the destination register
is also an input.

This also fixes a bug in which we failed to clear the high bits
of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-05-14 14:28:26 -07:00 • committed by Peter Maydell
parent fc417e5b57
commit a04b68e1d4
6 changed files with 138 additions and 67 deletions
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27
target/arm/translate.c
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@ -6350,22 +6350,23 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
return 1;
}
ptr1 = vfp_reg_ptr(true, rd);
ptr2 = vfp_reg_ptr(true, rm);
/* Bit 6 is the lowest opcode bit; it distinguishes between
* encryption (AESE/AESMC) and decryption (AESD/AESIMC)
*/
tmp3 = tcg_const_i32(extract32(insn, 6, 1));
/*
* Bit 6 is the lowest opcode bit; it distinguishes
* between encryption (AESE/AESMC) and decryption
* (AESD/AESIMC).
*/
if (op == NEON_2RM_AESE) {
gen_helper_crypto_aese(ptr1, ptr2, tmp3);
tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aese);
} else {
gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aesmc);
}
tcg_temp_free_ptr(ptr1);
tcg_temp_free_ptr(ptr2);
tcg_temp_free_i32(tmp3);
break;
case NEON_2RM_SHA1H:
if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {