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target/openrisc: Tidy handling of delayed branches

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Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2016-04-05 18:00:33 -07:00
parent 24c328521b
commit a01deb36a6
5 changed files with 25 additions and 35 deletions
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12
target/openrisc/cpu.h
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@ -83,9 +83,6 @@ enum {
/* Version Register */
#define SPR_VR 0xFFFF003F
/* Internal flags, delay slot flag */
#define D_FLAG 1
/* Interrupt */
#define NR_IRQS 32
@ -298,8 +295,7 @@ typedef struct CPUOpenRISCState {
target_ulong lock_addr;
target_ulong lock_value;
uint32_t flags; /* cpu_flags, we only use it for exception
in solt so far. */
uint32_t dflag; /* In delay slot (boolean) */
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@ -392,14 +388,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
#include "exec/cpu-all.h"
#define TB_FLAGS_DFLAG 1
#define TB_FLAGS_OVE SR_OVE
static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
*pc = env->pc;
*cs_base = 0;
/* D_FLAG -- branch instruction exception, OVE overflow trap enable. */
*flags = (env->flags & D_FLAG) | (env->sr & SR_OVE);
*flags = env->dflag | (env->sr & SR_OVE);
}
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)