motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-01 06:43:53 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/pci-host: Fix x86 Host Bridges 64bit PCI hole

Browse source 
Currently there is no MMIO range over 4G
reserved for PCI hotplug. Since the 32bit PCI hole
depends on the number of cold-plugged PCI devices
and other factors, it is very possible is too small
to hotplug PCI devices with large BARs.

Fix it by reserving 2G for I4400FX chipset
in order to comply with older Win32 Guest OSes
and 32G for Q35 chipset.

Even if the new defaults of pci-hole64-size will appear in
"info qtree" also for older machines, the property was
not implemented so no changes will be visible to guests.

Note this is a regression since prev QEMU versions had
some range reserved for 64bit PCI hotplug.

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Marcel Apfelbaum 2017-11-11 17:25:00 +02:00 • committed by Michael S. Tsirkin
parent d06bce95ff
commit 9fa99d2519
5 changed files with 101 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

10
include/hw/i386/pc.h
View file

@ -238,7 +238,6 @@ void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
@ -249,6 +248,7 @@ void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
MemoryRegion **ram_memory);
uint64_t pc_pci_hole64_start(void);
qemu_irq pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
@ -375,6 +375,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = TYPE_X86_CPU,\
.property = "x-hv-max-vps",\
.value = "0x40",\
},{\
.driver = "i440FX-pcihost",\
.property = "x-pci-hole64-fix",\
.value = "off",\
},{\
.driver = "q35-pcihost",\
.property = "x-pci-hole64-fix",\
.value = "off",\
},
#define PC_COMPAT_2_9 \

1
include/hw/pci-host/q35.h
View file

@ -68,6 +68,7 @@ typedef struct Q35PCIHost {
PCIExpressHost parent_obj;
/*< public >*/
bool pci_hole64_fix;
MCHPCIState mch;
} Q35PCIHost;