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https://github.com/Motorhead1991/qemu.git
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update Linux headers to 4.16-rc5
Note that VIRTIO_GPU_CAPSET_VIRGL2 was added manually so it has to be added manually after re-running scripts/update-linux-headers.sh. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
fb5fff1588
commit
9f2d175db5
16 changed files with 930 additions and 416 deletions
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@ -594,6 +594,7 @@
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#define BTN_DPAD_RIGHT 0x223
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#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
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#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */
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#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
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#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
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@ -18,10 +18,21 @@
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/*
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* The event structure itself
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* Note that __USE_TIME_BITS64 is defined by libc based on
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* application's request to use 64 bit time_t.
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*/
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struct input_event {
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#if (HOST_LONG_BITS != 32 || !defined(__USE_TIME_BITS64)) && !defined(__KERNEL)
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struct timeval time;
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#define input_event_sec time.tv_sec
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#define input_event_usec time.tv_usec
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#else
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__kernel_ulong_t __sec;
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__kernel_ulong_t __usec;
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#define input_event_sec __sec
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#define input_event_usec __usec
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#endif
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uint16_t type;
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uint16_t code;
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int32_t value;
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@ -622,15 +622,19 @@
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* safely.
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*/
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */
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#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
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#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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@ -966,26 +970,28 @@
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/* Downstream Port Containment */
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#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
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#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */
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#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
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#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
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#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
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#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
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#define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */
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#define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */
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#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */
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#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */
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#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */
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#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
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#define PCI_EXP_DPC_CTL 6 /* DPC control */
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#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */
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#define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */
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#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
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#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
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#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
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#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */
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#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */
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#define PCI_EXP_DPC_RP_BUSY 0x10 /* Root Port Busy */
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#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
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#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */
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#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */
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#define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */
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#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
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#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
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#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */
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#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */
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#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
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#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
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#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
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@ -57,6 +57,8 @@
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* Steering */
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#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
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#define VIRTIO_NET_F_SPEED_DUPLEX 63 /* Device set linkspeed and duplex */
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#ifndef VIRTIO_NET_NO_LEGACY
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#define VIRTIO_NET_F_GSO 6 /* Host handles pkts w/ any GSO type */
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#endif /* VIRTIO_NET_NO_LEGACY */
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@ -76,6 +78,17 @@ struct virtio_net_config {
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uint16_t max_virtqueue_pairs;
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/* Default maximum transmit unit advice */
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uint16_t mtu;
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/*
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* speed, in units of 1Mb. All values 0 to INT_MAX are legal.
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* Any other value stands for unknown.
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*/
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uint32_t speed;
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/*
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* 0x00 - half duplex
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* 0x01 - full duplex
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* Any other value stands for unknown.
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*/
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uint8_t duplex;
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} QEMU_PACKED;
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/*
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@ -78,7 +78,7 @@ struct vring_avail {
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__virtio16 ring[];
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};
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/* u32 is used here for ids for padding reasons. */
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/* uint32_t is used here for ids for padding reasons. */
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struct vring_used_elem {
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/* Index of start of used descriptor chain. */
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__virtio32 id;
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@ -1,3 +1,4 @@
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
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/*
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* Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
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*
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@ -51,12 +52,14 @@
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#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
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#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
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#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
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#define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */
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#define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */
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#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */
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#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */
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#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
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#define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */
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#define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */
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#define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */
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#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */
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#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */
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#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */
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#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */
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#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */
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enum pvrdma_wr_opcode {
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PVRDMA_WR_RDMA_WRITE,
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