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ppc patch queue 2019-04-26
Here's the first ppc target pull request for qemu-4.1. This has a
number of things that have accumulated while qemu-4.0 was frozen.
* A number of emulated MMU improvements from Ben Herrenschmidt
* Assorted cleanups fro Greg Kurz
* A large set of mostly mechanical cleanups from me to make target/ppc
much closer to compliant with the modern coding style
* Support for passthrough of NVIDIA GPUs using NVLink2
As well as some other assorted fixes.
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190426' into staging
ppc patch queue 2019-04-26
Here's the first ppc target pull request for qemu-4.1. This has a
number of things that have accumulated while qemu-4.0 was frozen.
* A number of emulated MMU improvements from Ben Herrenschmidt
* Assorted cleanups fro Greg Kurz
* A large set of mostly mechanical cleanups from me to make target/ppc
much closer to compliant with the modern coding style
* Support for passthrough of NVIDIA GPUs using NVLink2
As well as some other assorted fixes.
# gpg: Signature made Fri 26 Apr 2019 07:02:19 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.1-20190426: (36 commits)
target/ppc: improve performance of large BAT invalidations
ppc/hash32: Rework R and C bit updates
ppc/hash64: Rework R and C bit updates
ppc/spapr: Use proper HPTE accessors for H_READ
target/ppc: Don't check UPRT in radix mode when in HV real mode
target/ppc/kvm: Convert DPRINTF to traces
target/ppc/trace-events: Fix trivial typo
spapr: Drop duplicate PCI swizzle code
spapr_pci: Get rid of duplicate code for node name creation
target/ppc: Style fixes for translate/spe-impl.inc.c
target/ppc: Style fixes for translate/vmx-impl.inc.c
target/ppc: Style fixes for translate/vsx-impl.inc.c
target/ppc: Style fixes for translate/fp-impl.inc.c
target/ppc: Style fixes for translate.c
target/ppc: Style fixes for translate_init.inc.c
target/ppc: Style fixes for monitor.c
target/ppc: Style fixes for mmu_helper.c
target/ppc: Style fixes for mmu-hash64.[ch]
target/ppc: Style fixes for mmu-hash32.[ch]
target/ppc: Style fixes for misc_helper.c
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
9ec34ecc97
45 changed files with 2152 additions and 973 deletions
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@ -87,6 +87,9 @@ struct SpaprPhbState {
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uint32_t mig_liobn;
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hwaddr mig_mem_win_addr, mig_mem_win_size;
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hwaddr mig_io_win_addr, mig_io_win_size;
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hwaddr nv2_gpa_win_addr;
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hwaddr nv2_atsd_win_addr;
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struct spapr_phb_pci_nvgpu_config *nvgpus;
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};
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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@ -105,6 +108,22 @@ struct SpaprPhbState {
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT
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#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */
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/* Max number of these GPUsper a physical box */
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#define NVGPU_MAX_NUM 6
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/* Max number of NVLinks per GPU in any physical box */
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#define NVGPU_MAX_LINKS 3
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/*
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* GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB
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* which is enough. We do not need DMA for ATSD so we put them at 128TiB.
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*/
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#define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB)
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#define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
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64 * KiB)
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static inline qemu_irq spapr_phb_lsi_qirq(struct SpaprPhbState *phb, int pin)
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{
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SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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@ -135,6 +154,13 @@ int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
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int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
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int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
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void spapr_phb_vfio_reset(DeviceState *qdev);
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void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
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void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
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void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
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Error **errp);
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void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
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void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
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SpaprPhbState *sphb);
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#else
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static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
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{
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@ -161,6 +187,25 @@ static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
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static inline void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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}
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static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
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{
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}
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static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
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{
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}
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static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
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int bus_off, Error **errp)
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{
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}
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static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
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void *fdt)
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{
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}
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static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
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int offset,
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SpaprPhbState *sphb)
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{
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}
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#endif
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void spapr_phb_dma_reset(SpaprPhbState *sphb);
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@ -413,6 +413,10 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void pci_bus_irqs_cleanup(PCIBus *bus);
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int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
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/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
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static inline int pci_swizzle(int slot, int pin)
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{
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return (slot + pin) % PCI_NUM_PINS;
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}
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int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
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PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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@ -123,7 +123,8 @@ struct SpaprMachineClass {
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void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
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uint64_t *buid, hwaddr *pio,
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hwaddr *mmio32, hwaddr *mmio64,
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unsigned n_dma, uint32_t *liobns, Error **errp);
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unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
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hwaddr *nv2atsd, Error **errp);
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SpaprResizeHpt resize_hpt_default;
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SpaprCapabilities default_caps;
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SpaprIrq *irq;
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@ -199,6 +200,8 @@ struct SpaprMachineState {
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bool cmd_line_caps[SPAPR_CAP_NUM];
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SpaprCapabilities def, eff, mig;
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unsigned gpu_numa_id;
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};
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#define H_SUCCESS 0
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@ -672,6 +675,10 @@ typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets);
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void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
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static inline void spapr_rtas_unregister(int token)
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{
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spapr_rtas_register(token, NULL, NULL);
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}
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target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
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uint32_t token, uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets);
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@ -777,6 +784,8 @@ void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
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Error **errp);
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void spapr_clear_pending_events(SpaprMachineState *spapr);
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int spapr_max_server_number(SpaprMachineState *spapr);
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void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
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uint64_t pte0, uint64_t pte1);
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/* DRC callbacks. */
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void spapr_core_release(DeviceState *dev);
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