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https://github.com/Motorhead1991/qemu.git
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sparc merge (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1620 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
4787c71d17
commit
9e61bde56a
6 changed files with 735 additions and 173 deletions
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@ -195,15 +195,17 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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target_ulong virt_addr;
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target_phys_addr_t paddr;
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unsigned long vaddr;
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int error_code = 0, prot, ret = 0, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
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if (error_code == 0) {
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virt_addr = address & TARGET_PAGE_MASK;
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
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vaddr = address & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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#ifdef DEBUG_MMU
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printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
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#endif
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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}
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@ -276,6 +276,10 @@ void helper_ld_asi(int asi, int size, int sign)
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case 4:
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ret = ldl_phys(T0 & ~3);
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break;
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case 8:
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ret = ldl_phys(T0 & ~3);
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T0 = ldl_phys((T0 + 4) & ~3);
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break;
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}
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break;
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default:
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@ -396,6 +400,10 @@ void helper_st_asi(int asi, int size, int sign)
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default:
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stl_phys(T0 & ~3, T1);
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break;
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case 8:
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stl_phys(T0 & ~3, T1);
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stl_phys((T0 + 4) & ~3, T2);
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break;
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}
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}
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return;
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@ -1897,6 +1897,11 @@ static void disas_sparc_insn(DisasContext * dc)
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#else
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gen_op_xor_T1_T0();
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gen_op_wrpsr();
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save_state(dc);
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gen_op_next_insn();
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gen_op_movl_T0_0();
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gen_op_exit_tb();
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dc->is_br = 1;
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#endif
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}
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break;
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@ -2343,8 +2348,8 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_op_store_FT0_fpr(rd);
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break;
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case 0x21: /* load fsr */
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gen_op_ldst(ldf);
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gen_op_ldfsr();
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gen_op_store_FT0_fpr(rd);
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break;
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case 0x22: /* load quad fpreg */
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goto nfpu_insn;
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@ -2426,9 +2431,8 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_op_ldst(stf);
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break;
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case 0x25: /* stfsr, V9 stxfsr */
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gen_op_load_fpr_FT0(rd);
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// XXX
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gen_op_stfsr();
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gen_op_ldst(stf);
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break;
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case 0x26: /* stdfq */
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goto nfpu_insn;
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