motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-29 21:12:07 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/sparc: Move ADDRALIGN* to decodetree

Browse source 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 08:55:50 -07:00
parent 45bfed3b2c
commit 9e20ca9409
2 changed files with 34 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

3
target/sparc/insns.decode
View file

@ -252,6 +252,9 @@ RETRY 10 00001 111110 00000 0 0000000000000
ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r
ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r
ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
] ]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
} }

56
target/sparc/translate.c
View file

@ -2747,18 +2747,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
} }
} }
static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
{
TCGv tmp = tcg_temp_new();
tcg_gen_add_tl(tmp, s1, s2);
tcg_gen_andi_tl(dst, tmp, -8);
if (left) {
tcg_gen_neg_tl(tmp, tmp);
}
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
}
static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
{ {
TCGv t1, t2, shift; TCGv t1, t2, shift;
@ -4246,6 +4234,36 @@ TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8)
TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16)
TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32)
static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2)
{
#ifdef TARGET_SPARC64
TCGv tmp = tcg_temp_new();
tcg_gen_add_tl(tmp, s1, s2);
tcg_gen_andi_tl(dst, tmp, -8);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
#else
g_assert_not_reached();
#endif
}
static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2)
{
#ifdef TARGET_SPARC64
TCGv tmp = tcg_temp_new();
tcg_gen_add_tl(tmp, s1, s2);
tcg_gen_andi_tl(dst, tmp, -8);
tcg_gen_neg_tl(tmp, tmp);
tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
#else
g_assert_not_reached();
#endif
}
TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr)
TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl)
static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
{ {
TCGv dst, src1, src2; TCGv dst, src1, src2;
@ -5148,21 +5166,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x010: /* VIS I array8 */ case 0x010: /* VIS I array8 */
case 0x012: /* VIS I array16 */ case 0x012: /* VIS I array16 */
case 0x014: /* VIS I array32 */ case 0x014: /* VIS I array32 */
g_assert_not_reached(); /* in decodetree */
case 0x018: /* VIS I alignaddr */ case 0x018: /* VIS I alignaddr */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x01a: /* VIS I alignaddrl */ case 0x01a: /* VIS I alignaddrl */
CHECK_FPU_FEATURE(dc, VIS1); g_assert_not_reached(); /* in decodetree */
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x019: /* VIS II bmask */ case 0x019: /* VIS II bmask */
CHECK_FPU_FEATURE(dc, VIS2); CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1); cpu_src1 = gen_load_gpr(dc, rs1);