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target/xtensa: implement MEMCTL SR

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MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2016-11-11 22:40:18 -08:00
parent 4b37aaa879
commit 9e03ade441
6 changed files with 68 additions and 0 deletions
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target/xtensa/helper.h
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@ -23,6 +23,7 @@ DEF_HELPER_2(wsr_ccount, void, env, i32)
DEF_HELPER_2(update_ccompare, void, env, i32)
DEF_HELPER_1(check_interrupts, void, env)
DEF_HELPER_3(check_atomctl, void, env, i32, i32)
DEF_HELPER_2(wsr_memctl, void, env, i32)
DEF_HELPER_2(itlb_hit_test, void, env, i32)
DEF_HELPER_2(wsr_rasid, void, env, i32)