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Drop the deprecated lm32 target

Browse source 
Target lm32 was deprecated in commit d849800512, v5.2.0.  See there
for rationale.

Some of its code lives on in device models derived from milkymist
ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c.

Cc: Michael Walle <michael@walle.cc>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20210503084034.3804963-2-armbru@redhat.com>
Acked-by: Michael Walle <michael@walle.cc>
[Trivial conflicts resolved, reST markup fixed]
This commit is contained in:
Markus Armbruster 2021-05-03 10:40:33 +02:00
parent 09ec85176e
commit 9d49bcf699
150 changed files with 17 additions and 12234 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/qtest/machine-none-test.c
View file

@ -32,7 +32,6 @@ static struct arch2cpu cpus_map[] = {
{ "i386", "qemu32,apic-id=0" },
{ "alpha", "ev67" },
{ "cris", "crisv32" },
{ "lm32", "lm32-full" },
{ "m68k", "m5206" },
{ "microblaze", "any" },
{ "microblazeel", "any" },

6
tests/tcg/README
View file

@ -7,9 +7,3 @@ CRIS
====
The testsuite for CRIS is in tests/tcg/cris. You can run it
with "make test-cris".
LM32
====
The testsuite for LM32 is in tests/tcg/lm32. You can run it
with "make test-lm32".

2
tests/tcg/configure.sh
View file

@ -96,7 +96,7 @@ for target in $target_list; do
xtensa|xtensaeb)
arches=xtensa
;;
alpha|cris|hexagon|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64)
alpha|cris|hexagon|hppa|i386|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64)
arches=$target
;;
*)

106
tests/tcg/lm32/Makefile
View file

@ -1,106 +0,0 @@
-include ../../../config-host.mak
CROSS=lm32-elf-
SIM = qemu-system-lm32
SIMFLAGS = -M lm32-evr -nographic -semihosting -net none -kernel
CC = $(CROSS)gcc
AS = $(CROSS)as
AS = $(CC) -x assembler
SIZE = $(CROSS)size
LD = $(CC)
OBJCOPY = $(CROSS)objcopy
TSRC_PATH = $(SRC_PATH)/tests/tcg/lm32
LDFLAGS = -T$(TSRC_PATH)/linker.ld
ASFLAGS += -Wa,-I,$(TSRC_PATH)/
CRT = crt.o
HELPER = helper.o
TESTCASES += test_add.tst
TESTCASES += test_addi.tst
TESTCASES += test_and.tst
TESTCASES += test_andhi.tst
TESTCASES += test_andi.tst
TESTCASES += test_b.tst
TESTCASES += test_be.tst
TESTCASES += test_bg.tst
TESTCASES += test_bge.tst
TESTCASES += test_bgeu.tst
TESTCASES += test_bgu.tst
TESTCASES += test_bi.tst
TESTCASES += test_bne.tst
TESTCASES += test_break.tst
TESTCASES += test_bret.tst
TESTCASES += test_call.tst
TESTCASES += test_calli.tst
TESTCASES += test_cmpe.tst
TESTCASES += test_cmpei.tst
TESTCASES += test_cmpg.tst
TESTCASES += test_cmpgi.tst
TESTCASES += test_cmpge.tst
TESTCASES += test_cmpgei.tst
TESTCASES += test_cmpgeu.tst
TESTCASES += test_cmpgeui.tst
TESTCASES += test_cmpgu.tst
TESTCASES += test_cmpgui.tst
TESTCASES += test_cmpne.tst
TESTCASES += test_cmpnei.tst
TESTCASES += test_divu.tst
TESTCASES += test_eret.tst
TESTCASES += test_lb.tst
TESTCASES += test_lbu.tst
TESTCASES += test_lh.tst
TESTCASES += test_lhu.tst
TESTCASES += test_lw.tst
TESTCASES += test_modu.tst
TESTCASES += test_mul.tst
TESTCASES += test_muli.tst
TESTCASES += test_nor.tst
TESTCASES += test_nori.tst
TESTCASES += test_or.tst
TESTCASES += test_ori.tst
TESTCASES += test_orhi.tst
#TESTCASES += test_rcsr.tst
TESTCASES += test_ret.tst
TESTCASES += test_sb.tst
TESTCASES += test_scall.tst
TESTCASES += test_sextb.tst
TESTCASES += test_sexth.tst
TESTCASES += test_sh.tst
TESTCASES += test_sl.tst
TESTCASES += test_sli.tst
TESTCASES += test_sr.tst
TESTCASES += test_sri.tst
TESTCASES += test_sru.tst
TESTCASES += test_srui.tst
TESTCASES += test_sub.tst
TESTCASES += test_sw.tst
#TESTCASES += test_wcsr.tst
TESTCASES += test_xnor.tst
TESTCASES += test_xnori.tst
TESTCASES += test_xor.tst
TESTCASES += test_xori.tst
all: build
%.o: $(TSRC_PATH)/%.c
$(CC) $(CFLAGS) -c $< -o $@
%.o: $(TSRC_PATH)/%.S
$(AS) $(ASFLAGS) -c $< -o $@
%.tst: %.o $(TSRC_PATH)/macros.inc $(CRT) $(HELPER)
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $(HELPER) $< -o $@
build: $(TESTCASES)
check: $(TESTCASES:test_%.tst=check_%)
check_%: test_%.tst
@$(SIM) $(SIMFLAGS) $<
clean:
$(RM) -fr $(TESTCASES) $(CRT) $(HELPER)

84
tests/tcg/lm32/crt.S
View file

@ -1,84 +0,0 @@
.text
.global _start
_start:
_reset_handler:
xor r0, r0, r0
mvhi r1, hi(_start)
ori r1, r1, lo(_start)
wcsr eba, r1
wcsr deba, r1
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
bi _main
_breakpoint_handler:
ori r25, r25, 1
addi ra, ba, 4
ret
nop
nop
nop
nop
nop
_instruction_bus_error_handler:
ori r25, r25, 2
addi ra, ea, 4
ret
nop
nop
nop
nop
nop
_watchpoint_handler:
ori r25, r25, 4
addi ra, ba, 4
ret
nop
nop
nop
nop
nop
_data_bus_error_handler:
ori r25, r25, 8
addi ra, ea, 4
ret
nop
nop
nop
nop
nop
_divide_by_zero_handler:
ori r25, r25, 16
addi ra, ea, 4
ret
nop
nop
nop
nop
nop
_interrupt_handler:
ori r25, r25, 32
addi ra, ea, 4
ret
nop
nop
nop
nop
nop
_system_call_handler:
ori r25, r25, 64
addi ra, ea, 4
ret
nop
nop
nop
nop
nop

65
tests/tcg/lm32/helper.S
View file

@ -1,65 +0,0 @@
.text
.global _start, _write, _exit
.global _tc_fail, _tc_pass
_write:
addi sp, sp, -4
sw (sp+4), r8
mvi r8, 5
scall
lw r8, (sp+4)
addi sp, sp, 4
ret
_exit:
mvi r8, 1
scall
1:
bi 1b
_tc_pass:
.data
1:
.ascii "OK\n"
2:
.text
addi sp, sp, -16
sw (sp+4), ra
sw (sp+8), r1
sw (sp+12), r2
sw (sp+16), r3
mvi r1, 1
mvhi r2, hi(1b)
ori r2, r2, lo(1b)
mvi r3, (2b - 1b)
calli _write
lw r3, (sp+16)
lw r2, (sp+12)
lw r1, (sp+8)
lw ra, (sp+4)
addi sp, sp, 16
ret
_tc_fail:
.data
1:
.ascii "FAILED\n"
2:
.text
addi sp, sp, -16
sw (sp+4), ra
sw (sp+8), r1
sw (sp+12), r2
sw (sp+16), r3
sw (sp+4), ra
mvi r1, 1
mvhi r2, hi(1b)
ori r2, r2, lo(1b)
mvi r3, (2b - 1b)
calli _write
lw r3, (sp+16)
lw r2, (sp+12)
lw r1, (sp+8)
lw ra, (sp+4)
addi sp, sp, 16
ret

55
tests/tcg/lm32/linker.ld
View file

@ -1,55 +0,0 @@
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
ram : ORIGIN = 0x08000000, LENGTH = 0x04000000 /* 64M */
}
SECTIONS
{
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

90
tests/tcg/lm32/macros.inc
View file

@ -1,90 +0,0 @@
.equ MAX_TESTNAME_LEN, 32
.macro test_name name
.data
tn_\name:
.ascii "\name"
.space MAX_TESTNAME_LEN - (. - tn_\name), ' '
.text
.global \name
\name:
addi sp, sp, -12
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
mvi r1, 1
mvhi r2, hi(tn_\name)
ori r2, r2, lo(tn_\name)
mvi r3, MAX_TESTNAME_LEN
calli _write
lw r3, (sp+12)
lw r2, (sp+8)
lw r1, (sp+4)
addi sp, sp, 12
.endm
.macro load reg val
mvhi \reg, hi(\val)
ori \reg, \reg, lo(\val)
.endm
.macro tc_pass
calli _tc_pass
.endm
.macro tc_fail
addi r12, r12, 1
calli _tc_fail
.endm
.macro check_r3 val
mvhi r13, hi(\val)
ori r13, r13, lo(\val)
be r3, r13, 1f
tc_fail
bi 2f
1:
tc_pass
2:
.endm
.macro check_mem adr val
mvhi r13, hi(\adr)
ori r13, r13, lo(\adr)
mvhi r14, hi(\val)
ori r14, r14, lo(\val)
lw r13, (r13+0)
be r13, r14, 1f
tc_fail
bi 2f
1:
tc_pass
2:
.endm
.macro check_excp excp
andi r13, r25, \excp
bne r13, r0, 1f
tc_fail
bi 2f
1:
tc_pass
2:
.endm
.macro start
.global _main
.text
_main:
mvi r12, 0
.endm
.macro end
mv r1, r12
calli _exit
.endm
# base +
# 0 ctrl
# 4 pass/fail
# 8 ptr to test name

75
tests/tcg/lm32/test_add.S
View file

@ -1,75 +0,0 @@
.include "macros.inc"
start
test_name ADD_1
mvi r1, 0
mvi r2, 0
add r3, r1, r2
check_r3 0
test_name ADD_2
mvi r1, 0
mvi r2, 1
add r3, r1, r2
check_r3 1
test_name ADD_3
mvi r1, 1
mvi r2, 0
add r3, r1, r2
check_r3 1
test_name ADD_4
mvi r1, 1
mvi r2, -1
add r3, r1, r2
check_r3 0
test_name ADD_5
mvi r1, -1
mvi r2, 1
add r3, r1, r2
check_r3 0
test_name ADD_6
mvi r1, -1
mvi r2, 0
add r3, r1, r2
check_r3 -1
test_name ADD_7
mvi r1, 0
mvi r2, -1
add r3, r1, r2
check_r3 -1
test_name ADD_8
mvi r3, 2
add r3, r3, r3
check_r3 4
test_name ADD_9
mvi r1, 4
mvi r3, 2
add r3, r1, r3
check_r3 6
test_name ADD_10
mvi r1, 4
mvi r3, 2
add r3, r3, r1
check_r3 6
test_name ADD_11
mvi r1, 4
add r3, r1, r1
check_r3 8
test_name ADD_12
load r1 0x12345678
load r2 0xabcdef97
add r3, r1, r2
check_r3 0xbe02460f
end

56
tests/tcg/lm32/test_addi.S
View file

@ -1,56 +0,0 @@
.include "macros.inc"
start
test_name ADDI_1
mvi r1, 0
addi r3, r1, 0
check_r3 0
test_name ADDI_2
mvi r1, 0
addi r3, r1, 1
check_r3 1
test_name ADDI_3
mvi r1, 1
addi r3, r1, 0
check_r3 1
test_name ADDI_4
mvi r1, 1
addi r3, r1, -1
check_r3 0
test_name ADDI_5
mvi r1, -1
addi r3, r1, 1
check_r3 0
test_name ADDI_6
mvi r1, -1
addi r3, r1, 0
check_r3 -1
test_name ADDI_7
mvi r1, 0
addi r3, r1, -1
check_r3 -1
test_name ADDI_8
mvi r3, 4
addi r3, r3, 4
check_r3 8
test_name ADDI_9
mvi r3, 4
addi r3, r3, -4
check_r3 0
test_name ADDI_10
mvi r3, 4
addi r3, r3, -5
check_r3 -1
end

45
tests/tcg/lm32/test_and.S
View file

@ -1,45 +0,0 @@
.include "macros.inc"
start
test_name AND_1
mvi r1, 0
mvi r2, 0
and r3, r1, r2
check_r3 0
test_name AND_2
mvi r1, 0
mvi r2, 1
and r3, r1, r2
check_r3 0
test_name AND_3
mvi r1, 1
mvi r2, 1
and r3, r1, r2
check_r3 1
test_name AND_4
mvi r3, 7
and r3, r3, r3
check_r3 7
test_name AND_5
mvi r1, 7
and r3, r1, r1
check_r3 7
test_name AND_6
mvi r1, 7
mvi r3, 0
and r3, r1, r3
check_r3 0
test_name AND_7
load r1 0xaa55aa55
load r2 0x55aa55aa
and r3, r1, r2
check_r3 0
end

35
tests/tcg/lm32/test_andhi.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name ANDHI_1
mvi r1, 0
andhi r3, r1, 0
check_r3 0
test_name ANDHI_2
mvi r1, 1
andhi r3, r1, 1
check_r3 0
test_name ANDHI_3
load r1 0x000f0000
andhi r3, r1, 1
check_r3 0x00010000
test_name ANDHI_4
load r1 0xffffffff
andhi r3, r1, 0xffff
check_r3 0xffff0000
test_name ANDHI_5
load r1 0xffffffff
andhi r3, r1, 0
check_r3 0
test_name ANDHI_6
load r3 0x55aaffff
andhi r3, r3, 0xaaaa
check_r3 0x00aa0000
end

35
tests/tcg/lm32/test_andi.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name ANDI_1
mvi r1, 0
andi r3, r1, 0
check_r3 0
test_name ANDI_2
mvi r1, 1
andi r3, r1, 1
check_r3 1
test_name ANDI_3
load r1 0x000f0000
andi r3, r1, 1
check_r3 0
test_name ANDI_4
load r1 0xffffffff
andi r3, r1, 0xffff
check_r3 0xffff
test_name ANDI_5
load r1 0xffffffff
andi r3, r1, 0
check_r3 0
test_name ANDI_6
load r3 0xffff55aa
andi r3, r3, 0xaaaa
check_r3 0x000000aa
end

13
tests/tcg/lm32/test_b.S
View file

@ -1,13 +0,0 @@
.include "macros.inc"
start
test_name B_1
load r1 jump
b r1
tc_fail
end
jump:
tc_pass
end

48
tests/tcg/lm32/test_be.S
View file

@ -1,48 +0,0 @@
.include "macros.inc"
start
test_name BE_1
mvi r1, 0
mvi r2, 0
be r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BE_2
mvi r1, 1
mvi r2, 0
be r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BE_3
mvi r1, 0
mvi r2, 1
be r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
bi 2f
1:
tc_pass
bi 3f
2:
test_name BE_4
mvi r1, 1
mvi r2, 1
be r1, r2, 1b
tc_fail
3:
end

78
tests/tcg/lm32/test_bg.S
View file

@ -1,78 +0,0 @@
.include "macros.inc"
start
test_name BG_1
mvi r1, 0
mvi r2, 0
bg r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BG_2
mvi r1, 1
mvi r2, 0
bg r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BG_3
mvi r1, 0
mvi r2, 1
bg r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BG_4
mvi r1, 0
mvi r2, -1
bg r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BG_5
mvi r1, -1
mvi r2, 0
bg r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BG_6
mvi r1, -1
mvi r2, -1
bg r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
bi 2f
1:
tc_pass
bi 3f
2:
test_name BG_7
mvi r1, 1
mvi r2, 0
bg r1, r2, 1b
tc_fail
3:
end

78
tests/tcg/lm32/test_bge.S
View file

@ -1,78 +0,0 @@
.include "macros.inc"
start
test_name BGE_1
mvi r1, 0
mvi r2, 0
bge r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGE_2
mvi r1, 1
mvi r2, 0
bge r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGE_3
mvi r1, 0
mvi r2, 1
bge r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGE_4
mvi r1, 0
mvi r2, -1
bge r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGE_5
mvi r1, -1
mvi r2, 0
bge r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGE_6
mvi r1, -1
mvi r2, -1
bge r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
bi 2f
1:
tc_pass
bi 3f
2:
test_name BGE_7
mvi r1, 1
mvi r2, 0
bge r1, r2, 1b
tc_fail
3:
end

78
tests/tcg/lm32/test_bgeu.S
View file

@ -1,78 +0,0 @@
.include "macros.inc"
start
test_name BGEU_1
mvi r1, 0
mvi r2, 0
bgeu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGEU_2
mvi r1, 1
mvi r2, 0
bgeu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGEU_3
mvi r1, 0
mvi r2, 1
bgeu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGEU_4
mvi r1, 0
mvi r2, -1
bgeu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGEU_5
mvi r1, -1
mvi r2, 0
bgeu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGEU_6
mvi r1, -1
mvi r2, -1
bgeu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
bi 2f
1:
tc_pass
bi 3f
2:
test_name BGEU_7
mvi r1, 1
mvi r2, 0
bgeu r1, r2, 1b
tc_fail
3:
end

78
tests/tcg/lm32/test_bgu.S
View file

@ -1,78 +0,0 @@
.include "macros.inc"
start
test_name BGU_1
mvi r1, 0
mvi r2, 0
bgu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGU_2
mvi r1, 1
mvi r2, 0
bgu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGU_3
mvi r1, 0
mvi r2, 1
bgu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGU_4
mvi r1, 0
mvi r2, -1
bgu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BGU_5
mvi r1, -1
mvi r2, 0
bgu r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BGU_6
mvi r1, -1
mvi r2, -1
bgu r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
bi 2f
1:
tc_pass
bi 3f
2:
test_name BGU_7
mvi r1, 1
mvi r2, 0
bgu r1, r2, 1b
tc_fail
3:
end

23
tests/tcg/lm32/test_bi.S
View file

@ -1,23 +0,0 @@
.include "macros.inc"
start
test_name BI_1
bi jump
tc_fail
end
jump_back:
tc_pass
end
jump:
tc_pass
test_name BI_2
bi jump_back
tc_fail
end

48
tests/tcg/lm32/test_bne.S
View file

@ -1,48 +0,0 @@
.include "macros.inc"
start
test_name BNE_1
mvi r1, 0
mvi r2, 0
bne r1, r2, 1f
tc_pass
bi 2f
1:
tc_fail
2:
test_name BNE_2
mvi r1, 1
mvi r2, 0
bne r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
test_name BNE_3
mvi r1, 0
mvi r2, 1
bne r1, r2, 1f
tc_fail
bi 2f
1:
tc_pass
2:
bi 2f
1:
tc_fail
bi 3f
2:
test_name BNE_4
mvi r1, 1
mvi r2, 1
bne r1, r2, 1b
tc_pass
3:
end

20
tests/tcg/lm32/test_break.S
View file

@ -1,20 +0,0 @@
.include "macros.inc"
start
test_name BREAK_1
mvi r1, 1
wcsr IE, r1
insn:
break
check_excp 1
test_name BREAK_2
mv r3, ba
check_r3 insn
test_name BREAK_3
rcsr r3, IE
check_r3 4
end

38
tests/tcg/lm32/test_bret.S
View file

@ -1,38 +0,0 @@
.include "macros.inc"
start
test_name BRET_1
mvi r1, 4
wcsr IE, r1
load ba mark
bret
tc_fail
bi 1f
mark:
tc_pass
1:
test_name BRET_2
rcsr r3, IE
check_r3 5
test_name BRET_3
mvi r1, 0
wcsr IE, r1
load ba mark2
bret
tc_fail
bi 1f
mark2:
tc_pass
1:
test_name BRET_4
rcsr r3, IE
check_r3 0
end

16
tests/tcg/lm32/test_call.S
View file

@ -1,16 +0,0 @@
.include "macros.inc"
start
test_name CALL_1
load r1 mark
call r1
return:
tc_fail
end
mark:
mv r3, ra
check_r3 return
end

15
tests/tcg/lm32/test_calli.S
View file

@ -1,15 +0,0 @@
.include "macros.inc"
start
test_name CALLI_1
calli mark
return:
tc_fail
end
mark:
mv r3, ra
check_r3 return
end

40
tests/tcg/lm32/test_cmpe.S
View file

@ -1,40 +0,0 @@
.include "macros.inc"
start
test_name CMPE_1
mvi r1, 0
mvi r2, 0
cmpe r3, r1, r2
check_r3 1
test_name CMPE_2
mvi r1, 0
mvi r2, 1
cmpe r3, r1, r2
check_r3 0
test_name CMPE_3
mvi r1, 1
mvi r2, 0
cmpe r3, r1, r2
check_r3 0
test_name CMPE_4
mvi r3, 0
mvi r2, 1
cmpe r3, r3, r2
check_r3 0
test_name CMPE_5
mvi r3, 0
mvi r2, 0
cmpe r3, r3, r2
check_r3 1
test_name CMPE_6
mvi r3, 0
cmpe r3, r3, r3
check_r3 1
end

35
tests/tcg/lm32/test_cmpei.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name CMPEI_1
mvi r1, 0
cmpei r3, r1, 0
check_r3 1
test_name CMPEI_2
mvi r1, 0
cmpei r3, r1, 1
check_r3 0
test_name CMPEI_3
mvi r1, 1
cmpei r3, r1, 0
check_r3 0
test_name CMPEI_4
load r1 0xffffffff
cmpei r3, r1, -1
check_r3 1
test_name CMPEI_5
mvi r3, 0
cmpei r3, r3, 0
check_r3 1
test_name CMPEI_6
mvi r3, 0
cmpei r3, r3, 1
check_r3 0
end

64
tests/tcg/lm32/test_cmpg.S
View file

@ -1,64 +0,0 @@
.include "macros.inc"
start
test_name CMPG_1
mvi r1, 0
mvi r2, 0
cmpg r3, r1, r2
check_r3 0
test_name CMPG_2
mvi r1, 0
mvi r2, 1
cmpg r3, r1, r2
check_r3 0
test_name CMPG_3
mvi r1, 1
mvi r2, 0
cmpg r3, r1, r2
check_r3 1
test_name CMPG_4
mvi r1, 1
mvi r2, 1
cmpg r3, r1, r2
check_r3 0
test_name CMPG_5
mvi r1, 0
mvi r2, -1
cmpg r3, r1, r2
check_r3 1
test_name CMPG_6
mvi r1, -1
mvi r2, 0
cmpg r3, r1, r2
check_r3 0
test_name CMPG_7
mvi r1, -1
mvi r2, -1
cmpg r3, r1, r2
check_r3 0
test_name CMPG_8
mvi r3, 0
mvi r2, 1
cmpg r3, r3, r2
check_r3 0
test_name CMPG_9
mvi r3, 1
mvi r2, 0
cmpg r3, r3, r2
check_r3 1
test_name CMPG_10
mvi r3, 0
cmpg r3, r3, r3
check_r3 0
end

64
tests/tcg/lm32/test_cmpge.S
View file

@ -1,64 +0,0 @@
.include "macros.inc"
start
test_name CMPGE_1
mvi r1, 0
mvi r2, 0
cmpge r3, r1, r2
check_r3 1
test_name CMPGE_2
mvi r1, 0
mvi r2, 1
cmpge r3, r1, r2
check_r3 0
test_name CMPGE_3
mvi r1, 1
mvi r2, 0
cmpge r3, r1, r2
check_r3 1
test_name CMPGE_4
mvi r1, 1
mvi r2, 1
cmpge r3, r1, r2
check_r3 1
test_name CMPGE_5
mvi r1, 0
mvi r2, -1
cmpge r3, r1, r2
check_r3 1
test_name CMPGE_6
mvi r1, -1
mvi r2, 0
cmpge r3, r1, r2
check_r3 0
test_name CMPGE_7
mvi r1, -1
mvi r2, -1
cmpge r3, r1, r2
check_r3 1
test_name CMPGE_8
mvi r3, 0
mvi r2, 1
cmpge r3, r3, r2
check_r3 0
test_name CMPGE_9
mvi r3, 1
mvi r2, 0
cmpge r3, r3, r2
check_r3 1
test_name CMPGE_10
mvi r3, 0
cmpge r3, r3, r3
check_r3 1
end

70
tests/tcg/lm32/test_cmpgei.S
View file

@ -1,70 +0,0 @@
.include "macros.inc"
start
test_name CMPGEI_1
mvi r1, 0
cmpgei r3, r1, 0
check_r3 1
test_name CMPGEI_2
mvi r1, 0
cmpgei r3, r1, 1
check_r3 0
test_name CMPGEI_3
mvi r1, 1
cmpgei r3, r1, 0
check_r3 1
test_name CMPGEI_4
mvi r1, 1
cmpgei r3, r1, 1
check_r3 1
test_name CMPGEI_5
mvi r1, 0
cmpgei r3, r1, -1
check_r3 1
test_name CMPGEI_6
mvi r1, -1
cmpgei r3, r1, 0
check_r3 0
test_name CMPGEI_7
mvi r1, -1
cmpgei r3, r1, -1
check_r3 1
test_name CMPGEI_8
mvi r3, 0
cmpgei r3, r3, 1
check_r3 0
test_name CMPGEI_9
mvi r3, 1
cmpgei r3, r3, 0
check_r3 1
test_name CMPGEI_10
mvi r3, 0
cmpgei r3, r3, 0
check_r3 1
test_name CMPGEI_11
mvi r1, 0
cmpgei r3, r1, -32768
check_r3 1
test_name CMPGEI_12
mvi r1, -1
cmpgei r3, r1, -32768
check_r3 1
test_name CMPGEI_13
mvi r1, -32768
cmpgei r3, r1, -32768
check_r3 1
end

64
tests/tcg/lm32/test_cmpgeu.S
View file

@ -1,64 +0,0 @@
.include "macros.inc"
start
test_name CMPGEU_1
mvi r1, 0
mvi r2, 0
cmpgeu r3, r1, r2
check_r3 1
test_name CMPGEU_2
mvi r1, 0
mvi r2, 1
cmpgeu r3, r1, r2
check_r3 0
test_name CMPGEU_3
mvi r1, 1
mvi r2, 0
cmpgeu r3, r1, r2
check_r3 1
test_name CMPGEU_4
mvi r1, 1
mvi r2, 1
cmpgeu r3, r1, r2
check_r3 1
test_name CMPGEU_5
mvi r1, 0
mvi r2, -1
cmpgeu r3, r1, r2
check_r3 0
test_name CMPGEU_6
mvi r1, -1
mvi r2, 0
cmpgeu r3, r1, r2
check_r3 1
test_name CMPGEU_7
mvi r1, -1
mvi r2, -1
cmpgeu r3, r1, r2
check_r3 1
test_name CMPGEU_8
mvi r3, 0
mvi r2, 1
cmpgeu r3, r3, r2
check_r3 0
test_name CMPGEU_9
mvi r3, 1
mvi r2, 0
cmpgeu r3, r3, r2
check_r3 1
test_name CMPGEU_10
mvi r3, 0
cmpgeu r3, r3, r3
check_r3 1
end

70
tests/tcg/lm32/test_cmpgeui.S
View file

@ -1,70 +0,0 @@
.include "macros.inc"
start
test_name CMPGEUI_1
mvi r1, 0
cmpgeui r3, r1, 0
check_r3 1
test_name CMPGEUI_2
mvi r1, 0
cmpgeui r3, r1, 1
check_r3 0
test_name CMPGEUI_3
mvi r1, 1
cmpgeui r3, r1, 0
check_r3 1
test_name CMPGEUI_4
mvi r1, 1
cmpgeui r3, r1, 1
check_r3 1
test_name CMPGEUI_5
mvi r1, 0
cmpgeui r3, r1, 0xffff
check_r3 0
test_name CMPGEUI_6
mvi r1, -1
cmpgeui r3, r1, 0
check_r3 1
test_name CMPGEUI_7
mvi r1, -1
cmpgeui r3, r1, 0xffff
check_r3 1
test_name CMPGEUI_8
mvi r3, 0
cmpgeui r3, r3, 1
check_r3 0
test_name CMPGEUI_9
mvi r3, 1
cmpgeui r3, r3, 0
check_r3 1
test_name CMPGEUI_10
mvi r3, 0
cmpgeui r3, r3, 0
check_r3 1
test_name CMPGEUI_11
mvi r1, 0
cmpgeui r3, r1, 0x8000
check_r3 0
test_name CMPGEUI_12
mvi r1, -1
cmpgeui r3, r1, 0x8000
check_r3 1
test_name CMPGEUI_13
ori r1, r0, 0x8000
cmpgeui r3, r1, 0x8000
check_r3 1
end

70
tests/tcg/lm32/test_cmpgi.S
View file

@ -1,70 +0,0 @@
.include "macros.inc"
start
test_name CMPGI_1
mvi r1, 0
cmpgi r3, r1, 0
check_r3 0
test_name CMPGI_2
mvi r1, 0
cmpgi r3, r1, 1
check_r3 0
test_name CMPGI_3
mvi r1, 1
cmpgi r3, r1, 0
check_r3 1
test_name CMPGI_4
mvi r1, 1
cmpgi r3, r1, 1
check_r3 0
test_name CMPGI_5
mvi r1, 0
cmpgi r3, r1, -1
check_r3 1
test_name CMPGI_6
mvi r1, -1
cmpgi r3, r1, 0
check_r3 0
test_name CMPGI_7
mvi r1, -1
cmpgi r3, r1, -1
check_r3 0
test_name CMPGI_8
mvi r3, 0
cmpgi r3, r3, 1
check_r3 0
test_name CMPGI_9
mvi r3, 1
cmpgi r3, r3, 0
check_r3 1
test_name CMPGI_10
mvi r3, 0
cmpgi r3, r3, 0
check_r3 0
test_name CMPGI_11
mvi r1, 0
cmpgi r3, r1, -32768
check_r3 1
test_name CMPGI_12
mvi r1, -1
cmpgi r3, r1, -32768
check_r3 1
test_name CMPGI_13
mvi r1, -32768
cmpgi r3, r1, -32768
check_r3 0
end

64
tests/tcg/lm32/test_cmpgu.S
View file

@ -1,64 +0,0 @@
.include "macros.inc"
start
test_name CMPGU_1
mvi r1, 0
mvi r2, 0
cmpgu r3, r1, r2
check_r3 0
test_name CMPGU_2
mvi r1, 0
mvi r2, 1
cmpgu r3, r1, r2
check_r3 0
test_name CMPGU_3
mvi r1, 1
mvi r2, 0
cmpgu r3, r1, r2
check_r3 1
test_name CMPGU_4
mvi r1, 1
mvi r2, 1
cmpgu r3, r1, r2
check_r3 0
test_name CMPGU_5
mvi r1, 0
mvi r2, -1
cmpgu r3, r1, r2
check_r3 0
test_name CMPGU_6
mvi r1, -1
mvi r2, 0
cmpgu r3, r1, r2
check_r3 1
test_name CMPGU_7
mvi r1, -1
mvi r2, -1
cmpgu r3, r1, r2
check_r3 0
test_name CMPGU_8
mvi r3, 0
mvi r2, 1
cmpgu r3, r3, r2
check_r3 0
test_name CMPGU_9
mvi r3, 1
mvi r2, 0
cmpgu r3, r3, r2
check_r3 1
test_name CMPGU_10
mvi r3, 0
cmpgu r3, r3, r3
check_r3 0
end

70
tests/tcg/lm32/test_cmpgui.S
View file

@ -1,70 +0,0 @@
.include "macros.inc"
start
test_name CMPGUI_1
mvi r1, 0
cmpgui r3, r1, 0
check_r3 0
test_name CMPGUI_2
mvi r1, 0
cmpgui r3, r1, 1
check_r3 0
test_name CMPGUI_3
mvi r1, 1
cmpgui r3, r1, 0
check_r3 1
test_name CMPGUI_4
mvi r1, 1
cmpgui r3, r1, 1
check_r3 0
test_name CMPGUI_5
mvi r1, 0
cmpgui r3, r1, 0xffff
check_r3 0
test_name CMPGUI_6
mvi r1, -1
cmpgui r3, r1, 0
check_r3 1
test_name CMPGUI_7
mvi r1, -1
cmpgui r3, r1, 0xffff
check_r3 1
test_name CMPGUI_8
mvi r3, 0
cmpgui r3, r3, 1
check_r3 0
test_name CMPGUI_9
mvi r3, 1
cmpgui r3, r3, 0
check_r3 1
test_name CMPGUI_10
mvi r3, 0
cmpgui r3, r3, 0
check_r3 0
test_name CMPGUI_11
mvi r1, 0
cmpgui r3, r1, 0x8000
check_r3 0
test_name CMPGUI_12
mvi r1, -1
cmpgui r3, r1, 0x8000
check_r3 1
test_name CMPGUI_13
ori r1, r0, 0x8000
cmpgui r3, r1, 0x8000
check_r3 0
end

40
tests/tcg/lm32/test_cmpne.S
View file

@ -1,40 +0,0 @@
.include "macros.inc"
start
test_name CMPNE_1
mvi r1, 0
mvi r2, 0
cmpne r3, r1, r2
check_r3 0
test_name CMPNE_2
mvi r1, 0
mvi r2, 1
cmpne r3, r1, r2
check_r3 1
test_name CMPNE_3
mvi r1, 1
mvi r2, 0
cmpne r3, r1, r2
check_r3 1
test_name CMPNE_4
mvi r3, 0
mvi r2, 1
cmpne r3, r3, r2
check_r3 1
test_name CMPNE_5
mvi r3, 0
mvi r2, 0
cmpne r3, r3, r2
check_r3 0
test_name CMPNE_6
mvi r3, 0
cmpne r3, r3, r3
check_r3 0
end

35
tests/tcg/lm32/test_cmpnei.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name CMPNEI_1
mvi r1, 0
cmpnei r3, r1, 0
check_r3 0
test_name CMPNEI_2
mvi r1, 0
cmpnei r3, r1, 1
check_r3 1
test_name CMPNEI_3
mvi r1, 1
cmpnei r3, r1, 0
check_r3 1
test_name CMPNEI_4
load r1 0xffffffff
cmpnei r3, r1, -1
check_r3 0
test_name CMPNEI_5
mvi r3, 0
cmpnei r3, r3, 0
check_r3 0
test_name CMPNEI_6
mvi r3, 0
cmpnei r3, r3, 1
check_r3 1
end

29
tests/tcg/lm32/test_divu.S
View file

@ -1,29 +0,0 @@
.include "macros.inc"
start
test_name DIVU_1
mvi r1, 0
mvi r2, 1
divu r3, r1, r2
check_r3 0
test_name DIVU_2
mvi r1, 1
mvi r2, 1
divu r3, r1, r2
check_r3 1
test_name DIVU_3
mvi r1, 0
mvi r2, 0
divu r3, r1, r2
check_excp 16
test_name DIVU_4
load r1 0xabcdef12
load r2 0x12345
divu r3, r1, r2
check_r3 0x9700
end

38
tests/tcg/lm32/test_eret.S
View file

@ -1,38 +0,0 @@
.include "macros.inc"
start
test_name ERET_1
mvi r1, 2
wcsr IE, r1
load ea mark
eret
tc_fail
bi 1f
mark:
tc_pass
1:
test_name ERET_2
rcsr r3, IE
check_r3 3
test_name ERET_3
mvi r1, 0
wcsr IE, r1
load ea mark2
eret
tc_fail
bi 1f
mark2:
tc_pass
1:
test_name ERET_4
rcsr r3, IE
check_r3 0
end

49
tests/tcg/lm32/test_lb.S
View file

@ -1,49 +0,0 @@
.include "macros.inc"
start
test_name LB_1
load r1 data
lb r3, (r1+0)
check_r3 0x7e
test_name LB_2
load r1 data
lb r3, (r1+1)
check_r3 0x7f
test_name LB_3
load r1 data
lb r3, (r1+-1)
check_r3 0x7d
test_name LB_4
load r1 data_msb
lb r3, (r1+0)
check_r3 0xfffffffe
test_name LB_5
load r1 data_msb
lb r3, (r1+1)
check_r3 0xffffffff
test_name LB_6
load r1 data_msb
lb r3, (r1+-1)
check_r3 0xfffffffd
test_name LB_7
load r3 data
lb r3, (r3+0)
check_r3 0x7e
end
.data
.align 4
.byte 0x7a, 0x7b, 0x7c, 0x7d
data:
.byte 0x7e, 0x7f, 0x70, 0x71
.byte 0xfa, 0xfb, 0xfc, 0xfd
data_msb:
.byte 0xfe, 0xff, 0xf0, 0xf1

49
tests/tcg/lm32/test_lbu.S
View file

@ -1,49 +0,0 @@
.include "macros.inc"
start
test_name LBU_1
load r1 data
lbu r3, (r1+0)
check_r3 0x7e
test_name LBU_2
load r1 data
lbu r3, (r1+1)
check_r3 0x7f
test_name LBU_3
load r1 data
lbu r3, (r1+-1)
check_r3 0x7d
test_name LBU_4
load r1 data_msb
lbu r3, (r1+0)
check_r3 0xfe
test_name LBU_5
load r1 data_msb
lbu r3, (r1+1)
check_r3 0xff
test_name LBU_6
load r1 data_msb
lbu r3, (r1+-1)
check_r3 0xfd
test_name LBU_7
load r3 data
lbu r3, (r3+0)
check_r3 0x7e
end
.data
.align 4
.byte 0x7a, 0x7b, 0x7c, 0x7d
data:
.byte 0x7e, 0x7f, 0x70, 0x71
.byte 0xfa, 0xfb, 0xfc, 0xfd
data_msb:
.byte 0xfe, 0xff, 0xf0, 0xf1

49
tests/tcg/lm32/test_lh.S
View file

@ -1,49 +0,0 @@
.include "macros.inc"
start
test_name LH_1
load r1 data
lh r3, (r1+0)
check_r3 0x7e7f
test_name LH_2
load r1 data
lh r3, (r1+2)
check_r3 0x7071
test_name LH_3
load r1 data
lh r3, (r1+-2)
check_r3 0x7c7d
test_name LH_4
load r1 data_msb
lh r3, (r1+0)
check_r3 0xfffffeff
test_name LH_5
load r1 data_msb
lh r3, (r1+2)
check_r3 0xfffff0f1
test_name LH_6
load r1 data_msb
lh r3, (r1+-2)
check_r3 0xfffffcfd
test_name LH_7
load r3 data
lh r3, (r3+0)
check_r3 0x7e7f
end
.data
.align 4
.byte 0x7a, 0x7b, 0x7c, 0x7d
data:
.byte 0x7e, 0x7f, 0x70, 0x71
.byte 0xfa, 0xfb, 0xfc, 0xfd
data_msb:
.byte 0xfe, 0xff, 0xf0, 0xf1

49
tests/tcg/lm32/test_lhu.S
View file

@ -1,49 +0,0 @@
.include "macros.inc"
start
test_name LHU_1
load r1 data
lhu r3, (r1+0)
check_r3 0x7e7f
test_name LHU_2
load r1 data
lhu r3, (r1+2)
check_r3 0x7071
test_name LHU_3
load r1 data
lhu r3, (r1+-2)
check_r3 0x7c7d
test_name LHU_4
load r1 data_msb
lhu r3, (r1+0)
check_r3 0xfeff
test_name LHU_5
load r1 data_msb
lhu r3, (r1+2)
check_r3 0xf0f1
test_name LHU_6
load r1 data_msb
lhu r3, (r1+-2)
check_r3 0xfcfd
test_name LHU_7
load r3 data
lhu r3, (r3+0)
check_r3 0x7e7f
end
.data
.align 4
.byte 0x7a, 0x7b, 0x7c, 0x7d
data:
.byte 0x7e, 0x7f, 0x70, 0x71
.byte 0xfa, 0xfb, 0xfc, 0xfd
data_msb:
.byte 0xfe, 0xff, 0xf0, 0xf1

32
tests/tcg/lm32/test_lw.S
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@ -1,32 +0,0 @@
.include "macros.inc"
start
test_name LW_1
load r1 data
lw r3, (r1+0)
check_r3 0x7e7f7071
test_name LW_2
load r1 data
lw r3, (r1+4)
check_r3 0x72737475
test_name LW_3
load r1 data
lw r3, (r1+-4)
check_r3 0x7a7b7c7d
test_name LW_4
load r3 data
lw r3, (r3+0)
check_r3 0x7e7f7071
end
.data
.align 4
.byte 0x7a, 0x7b, 0x7c, 0x7d
data:
.byte 0x7e, 0x7f, 0x70, 0x71
.byte 0x72, 0x73, 0x74, 0x75

35
tests/tcg/lm32/test_modu.S
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@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name MODU_1
mvi r1, 0
mvi r2, 1
modu r3, r1, r2
check_r3 0
test_name MODU_2
mvi r1, 1
mvi r2, 1
modu r3, r1, r2
check_r3 0
test_name MODU_3
mvi r1, 3
mvi r2, 2
modu r3, r1, r2
check_r3 1
test_name MODU_4
mvi r1, 0
mvi r2, 0
modu r3, r1, r2
check_excp 16
test_name MODU_5
load r1 0xabcdef12
load r2 0x12345
modu r3, r1, r2
check_r3 0x3c12
end

70
tests/tcg/lm32/test_mul.S
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@ -1,70 +0,0 @@
.include "macros.inc"
start
test_name MUL_1
mvi r1, 0
mvi r2, 0
mul r3, r1, r2
check_r3 0
test_name MUL_2
mvi r1, 1
mvi r2, 0
mul r3, r1, r2
check_r3 0
test_name MUL_3
mvi r1, 0
mvi r2, 1
mul r3, r1, r2
check_r3 0
test_name MUL_4
mvi r1, 1
mvi r2, 1
mul r3, r1, r2
check_r3 1
test_name MUL_5
mvi r1, 2
mvi r2, -1
mul r3, r1, r2
check_r3 -2
test_name MUL_6
mvi r1, -2
mvi r2, -1
mul r3, r1, r2
check_r3 2
test_name MUL_7
mvi r1, 0x1234
mvi r2, 0x789
mul r3, r1, r2
check_r3 0x8929d4
test_name MUL_8
mvi r3, 4
mul r3, r3, r3
check_r3 16
test_name MUL_9
mvi r2, 2
mvi r3, 4
mul r3, r3, r2
check_r3 8
test_name MUL_10
load r1 0x12345678
load r2 0x7bcdef12
mul r3, r1, r2
check_r3 0xa801c70
test_name MUL_11
load r1 0x12345678
load r2 0xabcdef12
mul r3, r1, r2
check_r3 0x8a801c70
end

45
tests/tcg/lm32/test_muli.S
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@ -1,45 +0,0 @@
.include "macros.inc"
start
test_name MULI_1
mvi r1, 0
muli r3, r1, 0
check_r3 0
test_name MULI_2
mvi r1, 1
muli r3, r1, 0
check_r3 0
test_name MULI_3
mvi r1, 0
muli r3, r1, 1
check_r3 0
test_name MULI_4
mvi r1, 1
muli r3, r1, 1
check_r3 1
test_name MULI_5
mvi r1, 2
muli r3, r1, -1
check_r3 -2
test_name MULI_6
mvi r1, -2
muli r3, r1, -1
check_r3 2
test_name MULI_7
mvi r1, 0x1234
muli r3, r1, 0x789
check_r3 0x8929d4
test_name MULI_8
mvi r3, 4
muli r3, r3, 4
check_r3 16
end

51
tests/tcg/lm32/test_nor.S
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@ -1,51 +0,0 @@
.include "macros.inc"
start
test_name NOR_1
mvi r1, 0
mvi r2, 0
nor r3, r1, r2
check_r3 0xffffffff
test_name NOR_2
mvi r1, 0
mvi r2, 1
nor r3, r1, r2
check_r3 0xfffffffe
test_name NOR_3
mvi r1, 1
mvi r2, 1
nor r3, r1, r2
check_r3 0xfffffffe
test_name NOR_4
mvi r1, 1
mvi r2, 0
nor r3, r1, r2
check_r3 0xfffffffe
test_name NOR_5
load r1 0xaa55aa55
load r2 0x55aa55aa
nor r3, r1, r2
check_r3 0
test_name NOR_6
load r1 0xaa550000
load r2 0x0000aa55
nor r3, r1, r2
check_r3 0x55aa55aa
test_name NOR_7
load r1 0xaa55aa55
nor r3, r1, r1
check_r3 0x55aa55aa
test_name NOR_8
load r3 0xaa55aa55
nor r3, r3, r3
check_r3 0x55aa55aa
end

35
tests/tcg/lm32/test_nori.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name NORI_1
mvi r1, 0
nori r3, r1, 0
check_r3 0xffffffff
test_name NORI_2
mvi r1, 0
nori r3, r1, 1
check_r3 0xfffffffe
test_name NORI_3
mvi r1, 1
nori r3, r1, 1
check_r3 0xfffffffe
test_name NORI_4
mvi r1, 1
nori r3, r1, 0
check_r3 0xfffffffe
test_name NORI_5
load r1 0xaa55aa55
nori r3, r1, 0x55aa
check_r3 0x55aa0000
test_name NORI_6
load r3 0xaa55aa55
nori r3, r3, 0x55aa
check_r3 0x55aa0000
end

51
tests/tcg/lm32/test_or.S
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@ -1,51 +0,0 @@
.include "macros.inc"
start
test_name OR_1
mvi r1, 0
mvi r2, 0
or r3, r1, r2
check_r3 0
test_name OR_2
mvi r1, 0
mvi r2, 1
or r3, r1, r2
check_r3 1
test_name OR_3
mvi r1, 1
mvi r2, 1
or r3, r1, r2
check_r3 1
test_name OR_4
mvi r1, 1
mvi r2, 0
or r3, r1, r2
check_r3 1
test_name OR_5
load r1 0xaa55aa55
load r2 0x55aa55aa
or r3, r1, r2
check_r3 0xffffffff
test_name OR_6
load r1 0xaa550000
load r2 0x0000aa55
or r3, r1, r2
check_r3 0xaa55aa55
test_name OR_7
load r1 0xaa55aa55
or r3, r1, r1
check_r3 0xaa55aa55
test_name OR_8
load r3 0xaa55aa55
or r3, r3, r3
check_r3 0xaa55aa55
end

35
tests/tcg/lm32/test_orhi.S
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@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name ORHI_1
mvi r1, 0
orhi r3, r1, 0
check_r3 0
test_name ORHI_2
mvi r1, 0
orhi r3, r1, 1
check_r3 0x00010000
test_name ORHI_3
load r1 0x00010000
orhi r3, r1, 1
check_r3 0x00010000
test_name ORHI_4
mvi r1, 1
orhi r3, r1, 0
check_r3 1
test_name ORHI_5
load r1 0xaa55aa55
orhi r3, r1, 0x55aa
check_r3 0xffffaa55
test_name ORHI_6
load r3 0xaa55aa55
orhi r3, r3, 0x55aa
check_r3 0xffffaa55
end

35
tests/tcg/lm32/test_ori.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name ORI_1
mvi r1, 0
ori r3, r1, 0
check_r3 0
test_name ORI_2
mvi r1, 0
ori r3, r1, 1
check_r3 1
test_name ORI_3
mvi r1, 1
ori r3, r1, 1
check_r3 1
test_name ORI_4
mvi r1, 1
ori r3, r1, 0
check_r3 1
test_name ORI_5
load r1 0xaa55aa55
ori r3, r1, 0x55aa
check_r3 0xaa55ffff
test_name ORI_6
load r3 0xaa55aa55
ori r3, r3, 0x55aa
check_r3 0xaa55ffff
end

14
tests/tcg/lm32/test_ret.S
View file

@ -1,14 +0,0 @@
.include "macros.inc"
start
test_name RET_1
load ra mark
ret
tc_fail
end
mark:
tc_pass
end

32
tests/tcg/lm32/test_sb.S
View file

@ -1,32 +0,0 @@
.include "macros.inc"
start
test_name SB_1
load r1 data
load r2 0xf0f1f2aa
sb (r1+0), r2
check_mem data 0xaa000000
test_name SB_2
load r1 data
load r2 0xf0f1f2bb
sb (r1+1), r2
check_mem data 0xaabb0000
test_name SB_3
load r1 data
load r2 0xf0f1f2cc
sb (r1+-1), r2
check_mem data0 0x000000cc
end
.data
.align 4
data0:
.byte 0, 0, 0, 0
data:
.byte 0, 0, 0, 0
data1:
.byte 0, 0, 0, 0

24
tests/tcg/lm32/test_scall.S
View file

@ -1,24 +0,0 @@
.include "macros.inc"
start
test_name SCALL_1
mvi r1, 1
wcsr IE, r1
# we are running in a semi hosted environment
# therefore we have to set r8 to some unused system
# call
mvi r8, 0
insn:
scall
check_excp 64
test_name SCALL_2
mv r3, ea
check_r3 insn
test_name SCALL_3
rcsr r3, IE
check_r3 2
end

20
tests/tcg/lm32/test_sextb.S
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@ -1,20 +0,0 @@
.include "macros.inc"
start
test_name SEXTB_1
mvi r1, 0
sextb r3, r1
check_r3 0
test_name SEXTB_2
mvi r1, 0x7f
sextb r3, r1
check_r3 0x0000007f
test_name SEXTB_3
mvi r1, 0x80
sextb r3, r1
check_r3 0xffffff80
end

20
tests/tcg/lm32/test_sexth.S
View file

@ -1,20 +0,0 @@
.include "macros.inc"
start
test_name SEXTH_1
mvi r1, 0
sexth r3, r1
check_r3 0
test_name SEXTH_2
load r1 0x7fff
sexth r3, r1
check_r3 0x00007fff
test_name SEXTH_3
load r1 0x8000
sexth r3, r1
check_r3 0xffff8000
end

32
tests/tcg/lm32/test_sh.S
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@ -1,32 +0,0 @@
.include "macros.inc"
start
test_name SH_1
load r1 data
load r2 0xf0f1aaaa
sh (r1+0), r2
check_mem data 0xaaaa0000
test_name SH_2
load r1 data
load r2 0xf0f1bbbb
sh (r1+2), r2
check_mem data 0xaaaabbbb
test_name SH_3
load r1 data
load r2 0xf0f1cccc
sh (r1+-2), r2
check_mem data0 0x0000cccc
end
.data
.align 4
data0:
.byte 0, 0, 0, 0
data:
.byte 0, 0, 0, 0
data1:
.byte 0, 0, 0, 0

45
tests/tcg/lm32/test_sl.S
View file

@ -1,45 +0,0 @@
.include "macros.inc"
start
test_name SL_1
mvi r1, 1
mvi r2, 0
sl r3, r1, r2
check_r3 1
test_name SL_2
mvi r1, 0
mvi r2, 1
sl r3, r1, r2
check_r3 0
test_name SL_3
mvi r1, 1
mvi r2, 31
sl r3, r1, r2
check_r3 0x80000000
test_name SL_4
mvi r1, 16
mvi r2, 31
sl r3, r1, r2
check_r3 0
test_name SL_5
mvi r1, 1
mvi r2, 34
sl r3, r1, r2
check_r3 4
test_name SL_6
mvi r1, 2
sl r3, r1, r1
check_r3 8
test_name SL_7
mvi r3, 2
sl r3, r3, r3
check_r3 8
end

30
tests/tcg/lm32/test_sli.S
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@ -1,30 +0,0 @@
.include "macros.inc"
start
test_name SLI_1
mvi r1, 1
sli r3, r1, 0
check_r3 1
test_name SLI_2
mvi r1, 0
sli r3, r1, 1
check_r3 0
test_name SLI_3
mvi r1, 1
sli r3, r1, 31
check_r3 0x80000000
test_name SLI_4
mvi r1, 16
sli r3, r1, 31
check_r3 0
test_name SLI_7
mvi r3, 2
sli r3, r3, 2
check_r3 8
end

57
tests/tcg/lm32/test_sr.S
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@ -1,57 +0,0 @@
.include "macros.inc"
start
test_name SR_1
mvi r1, 1
mvi r2, 0
sr r3, r1, r2
check_r3 1
test_name SR_2
mvi r1, 0
mvi r2, 1
sr r3, r1, r2
check_r3 0
test_name SR_3
load r1 0x40000000
mvi r2, 30
sr r3, r1, r2
check_r3 1
test_name SR_4
load r1 0x40000000
mvi r2, 31
sr r3, r1, r2
check_r3 0
test_name SR_5
mvi r1, 16
mvi r2, 34
sr r3, r1, r2
check_r3 4
test_name SR_6
mvi r1, 2
sr r3, r1, r1
check_r3 0
test_name SR_7
mvi r3, 2
sr r3, r3, r3
check_r3 0
test_name SR_8
mvi r1, 0xfffffff0
mvi r2, 2
sr r3, r1, r2
check_r3 0xfffffffc
test_name SR_9
mvi r1, 0xfffffff0
mvi r2, 4
sr r3, r1, r2
check_r3 0xffffffff
end

40
tests/tcg/lm32/test_sri.S
View file

@ -1,40 +0,0 @@
.include "macros.inc"
start
test_name SRI_1
mvi r1, 1
sri r3, r1, 0
check_r3 1
test_name SRI_2
mvi r1, 0
sri r3, r1, 1
check_r3 0
test_name SRI_3
load r1 0x40000000
sri r3, r1, 30
check_r3 1
test_name SRI_4
load r1 0x40000000
sri r3, r1, 31
check_r3 0
test_name SRI_5
mvi r3, 2
sri r3, r3, 2
check_r3 0
test_name SRI_6
mvi r1, 0xfffffff0
sri r3, r1, 2
check_r3 0xfffffffc
test_name SRI_7
mvi r1, 0xfffffff0
sri r3, r1, 4
check_r3 0xffffffff
end

57
tests/tcg/lm32/test_sru.S
View file

@ -1,57 +0,0 @@
.include "macros.inc"
start
test_name SRU_1
mvi r1, 1
mvi r2, 0
sru r3, r1, r2
check_r3 1
test_name SRU_2
mvi r1, 0
mvi r2, 1
sru r3, r1, r2
check_r3 0
test_name SRU_3
load r1 0x40000000
mvi r2, 30
sru r3, r1, r2
check_r3 1
test_name SRU_4
load r1 0x40000000
mvi r2, 31
sru r3, r1, r2
check_r3 0
test_name SRU_5
mvi r1, 16
mvi r2, 34
sru r3, r1, r2
check_r3 4
test_name SRU_6
mvi r1, 2
sru r3, r1, r1
check_r3 0
test_name SRU_7
mvi r3, 2
sru r3, r3, r3
check_r3 0
test_name SRU_8
mvi r1, 0xfffffff0
mvi r2, 2
sru r3, r1, r2
check_r3 0x3ffffffc
test_name SRU_9
mvi r1, 0xfffffff0
mvi r2, 4
sru r3, r1, r2
check_r3 0x0fffffff
end

40
tests/tcg/lm32/test_srui.S
View file

@ -1,40 +0,0 @@
.include "macros.inc"
start
test_name SRUI_1
mvi r1, 1
srui r3, r1, 0
check_r3 1
test_name SRUI_2
mvi r1, 0
srui r3, r1, 1
check_r3 0
test_name SRUI_3
load r1 0x40000000
srui r3, r1, 30
check_r3 1
test_name SRUI_4
load r1 0x40000000
srui r3, r1, 31
check_r3 0
test_name SRUI_5
mvi r3, 2
srui r3, r3, 2
check_r3 0
test_name SRUI_6
mvi r1, 0xfffffff0
srui r3, r1, 2
check_r3 0x3ffffffc
test_name SRUI_7
mvi r1, 0xfffffff0
srui r3, r1, 4
check_r3 0x0fffffff
end

75
tests/tcg/lm32/test_sub.S
View file

@ -1,75 +0,0 @@
.include "macros.inc"
start
test_name SUB_1
mvi r1, 0
mvi r2, 0
sub r3, r1, r2
check_r3 0
test_name SUB_2
mvi r1, 0
mvi r2, 1
sub r3, r1, r2
check_r3 -1
test_name SUB_3
mvi r1, 1
mvi r2, 0
sub r3, r1, r2
check_r3 1
test_name SUB_4
mvi r1, 1
mvi r2, -1
sub r3, r1, r2
check_r3 2
test_name SUB_5
mvi r1, -1
mvi r2, 1
sub r3, r1, r2
check_r3 -2
test_name SUB_6
mvi r1, -1
mvi r2, 0
sub r3, r1, r2
check_r3 -1
test_name SUB_7
mvi r1, 0
mvi r2, -1
sub r3, r1, r2
check_r3 1
test_name SUB_8
mvi r3, 2
sub r3, r3, r3
check_r3 0
test_name SUB_9
mvi r1, 4
mvi r3, 2
sub r3, r1, r3
check_r3 2
test_name SUB_10
mvi r1, 4
mvi r3, 2
sub r3, r3, r1
check_r3 -2
test_name SUB_11
mvi r1, 4
sub r3, r1, r1
check_r3 0
test_name SUB_12
load r1 0x12345678
load r2 0xabcdef97
sub r3, r1, r2
check_r3 0x666666e1
end

38
tests/tcg/lm32/test_sw.S
View file

@ -1,38 +0,0 @@
.include "macros.inc"
start
test_name SW_1
load r1 data
load r2 0xaabbccdd
sw (r1+0), r2
check_mem data 0xaabbccdd
test_name SW_2
load r1 data
load r2 0x00112233
sw (r1+4), r2
check_mem data1 0x00112233
test_name SW_3
load r1 data
load r2 0x44556677
sw (r1+-4), r2
check_mem data0 0x44556677
test_name SW_4
load r1 data
sw (r1+0), r1
lw r3, (r1+0)
check_r3 data
end
.data
.align 4
data0:
.byte 0, 0, 0, 0
data:
.byte 0, 0, 0, 0
data1:
.byte 0, 0, 0, 0

51
tests/tcg/lm32/test_xnor.S
View file

@ -1,51 +0,0 @@
.include "macros.inc"
start
test_name XNOR_1
mvi r1, 0
mvi r2, 0
xnor r3, r1, r2
check_r3 0xffffffff
test_name XNOR_2
mvi r1, 0
mvi r2, 1
xnor r3, r1, r2
check_r3 0xfffffffe
test_name XNOR_3
mvi r1, 1
mvi r2, 1
xnor r3, r1, r2
check_r3 0xffffffff
test_name XNOR_4
mvi r1, 1
mvi r2, 0
xnor r3, r1, r2
check_r3 0xfffffffe
test_name XNOR_5
load r1 0xaa55aa55
load r2 0x55aa55aa
xnor r3, r1, r2
check_r3 0
test_name XNOR_6
load r1 0xaa550000
load r2 0x0000aa55
xnor r3, r1, r2
check_r3 0x55aa55aa
test_name XNOR_7
load r1 0xaa55aa55
xnor r3, r1, r1
check_r3 0xffffffff
test_name XNOR_8
load r3 0xaa55aa55
xnor r3, r3, r3
check_r3 0xffffffff
end

35
tests/tcg/lm32/test_xnori.S
View file

@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name XNORI_1
mvi r1, 0
xnori r3, r1, 0
check_r3 0xffffffff
test_name XNORI_2
mvi r1, 0
xnori r3, r1, 1
check_r3 0xfffffffe
test_name XNORI_3
mvi r1, 1
xnori r3, r1, 1
check_r3 0xffffffff
test_name XNORI_4
mvi r1, 1
xnori r3, r1, 0
check_r3 0xfffffffe
test_name XNORI_5
load r1 0xaa55aa55
xnori r3, r1, 0x5555
check_r3 0x55aa00ff
test_name XNORI_6
load r3 0xaa55aa55
xnori r3, r3, 0x5555
check_r3 0x55aa00ff
end

51
tests/tcg/lm32/test_xor.S
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@ -1,51 +0,0 @@
.include "macros.inc"
start
test_name XOR_1
mvi r1, 0
mvi r2, 0
xor r3, r1, r2
check_r3 0
test_name XOR_2
mvi r1, 0
mvi r2, 1
xor r3, r1, r2
check_r3 1
test_name XOR_3
mvi r1, 1
mvi r2, 1
xor r3, r1, r2
check_r3 0
test_name XOR_4
mvi r1, 1
mvi r2, 0
xor r3, r1, r2
check_r3 1
test_name XOR_5
load r1 0xaa55aa55
load r2 0x55aa55aa
xor r3, r1, r2
check_r3 0xffffffff
test_name XOR_6
load r1 0xaa550000
load r2 0x0000aa55
xor r3, r1, r2
check_r3 0xaa55aa55
test_name XOR_7
load r1 0xaa55aa55
xor r3, r1, r1
check_r3 0
test_name XOR_8
load r3 0xaa55aa55
xor r3, r3, r3
check_r3 0
end

35
tests/tcg/lm32/test_xori.S
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@ -1,35 +0,0 @@
.include "macros.inc"
start
test_name XORI_1
mvi r1, 0
xori r3, r1, 0
check_r3 0
test_name XORI_2
mvi r1, 0
xori r3, r1, 1
check_r3 1
test_name XORI_3
mvi r1, 1
xori r3, r1, 1
check_r3 0
test_name XORI_4
mvi r1, 1
xori r3, r1, 0
check_r3 1
test_name XORI_5
load r1 0xaa55aa55
xori r3, r1, 0x5555
check_r3 0xaa55ff00
test_name XORI_6
load r3 0xaa55aa55
xori r3, r3, 0x5555
check_r3 0xaa55ff00
end