motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

Drop the deprecated lm32 target

Browse source 
Target lm32 was deprecated in commit d849800512, v5.2.0.  See there
for rationale.

Some of its code lives on in device models derived from milkymist
ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c.

Cc: Michael Walle <michael@walle.cc>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20210503084034.3804963-2-armbru@redhat.com>
Acked-by: Michael Walle <michael@walle.cc>
[Trivial conflicts resolved, reST markup fixed]
This commit is contained in:
Markus Armbruster 2021-05-03 10:40:33 +02:00
parent 09ec85176e
commit 9d49bcf699
150 changed files with 17 additions and 12234 deletions
Download patch file Download diff file Expand all files Collapse all files

166
hw/char/lm32_juart.c
View file

@ -1,166 +0,0 @@
/*
* LatticeMico32 JTAG UART model.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "trace.h"
#include "chardev/char-fe.h"
#include "hw/char/lm32_juart.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "qom/object.h"
enum {
LM32_JUART_MIN_SAVE_VERSION = 0,
LM32_JUART_CURRENT_SAVE_VERSION = 0,
LM32_JUART_MAX_SAVE_VERSION = 0,
};
enum {
JTX_FULL = (1<<8),
};
enum {
JRX_FULL = (1<<8),
};
OBJECT_DECLARE_SIMPLE_TYPE(LM32JuartState, LM32_JUART)
struct LM32JuartState {
SysBusDevice parent_obj;
CharBackend chr;
uint32_t jtx;
uint32_t jrx;
};
uint32_t lm32_juart_get_jtx(DeviceState *d)
{
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_get_jtx(s->jtx);
return s->jtx;
}
uint32_t lm32_juart_get_jrx(DeviceState *d)
{
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_get_jrx(s->jrx);
return s->jrx;
}
void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
{
LM32JuartState *s = LM32_JUART(d);
unsigned char ch = jtx & 0xff;
trace_lm32_juart_set_jtx(s->jtx);
s->jtx = jtx;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
void lm32_juart_set_jrx(DeviceState *d, uint32_t jtx)
{
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_set_jrx(s->jrx);
s->jrx &= ~JRX_FULL;
}
static void juart_rx(void *opaque, const uint8_t *buf, int size)
{
LM32JuartState *s = opaque;
s->jrx = *buf | JRX_FULL;
}
static int juart_can_rx(void *opaque)
{
LM32JuartState *s = opaque;
return !(s->jrx & JRX_FULL);
}
static void juart_event(void *opaque, QEMUChrEvent event)
{
}
static void juart_reset(DeviceState *d)
{
LM32JuartState *s = LM32_JUART(d);
s->jtx = 0;
s->jrx = 0;
}
static void lm32_juart_realize(DeviceState *dev, Error **errp)
{
LM32JuartState *s = LM32_JUART(dev);
qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
juart_event, NULL, s, NULL, true);
}
static const VMStateDescription vmstate_lm32_juart = {
.name = "lm32-juart",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(jtx, LM32JuartState),
VMSTATE_UINT32(jrx, LM32JuartState),
VMSTATE_END_OF_LIST()
}
};
static Property lm32_juart_properties[] = {
DEFINE_PROP_CHR("chardev", LM32JuartState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void lm32_juart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = juart_reset;
dc->vmsd = &vmstate_lm32_juart;
device_class_set_props(dc, lm32_juart_properties);
dc->realize = lm32_juart_realize;
}
static const TypeInfo lm32_juart_info = {
.name = TYPE_LM32_JUART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32JuartState),
.class_init = lm32_juart_class_init,
};
static void lm32_juart_register_types(void)
{
type_register_static(&lm32_juart_info);
}
type_init(lm32_juart_register_types)

314
hw/char/lm32_uart.c
View file

@ -1,314 +0,0 @@
/*
* QEMU model of the LatticeMico32 UART block.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*
* Specification available at:
* http://www.latticesemi.com/documents/mico32uart.pdf
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "chardev/char-fe.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
R_RXTX = 0,
R_IER,
R_IIR,
R_LCR,
R_MCR,
R_LSR,
R_MSR,
R_DIV,
R_MAX
};
enum {
IER_RBRI = (1<<0),
IER_THRI = (1<<1),
IER_RLSI = (1<<2),
IER_MSI = (1<<3),
};
enum {
IIR_STAT = (1<<0),
IIR_ID0 = (1<<1),
IIR_ID1 = (1<<2),
};
enum {
LCR_WLS0 = (1<<0),
LCR_WLS1 = (1<<1),
LCR_STB = (1<<2),
LCR_PEN = (1<<3),
LCR_EPS = (1<<4),
LCR_SP = (1<<5),
LCR_SB = (1<<6),
};
enum {
MCR_DTR = (1<<0),
MCR_RTS = (1<<1),
};
enum {
LSR_DR = (1<<0),
LSR_OE = (1<<1),
LSR_PE = (1<<2),
LSR_FE = (1<<3),
LSR_BI = (1<<4),
LSR_THRE = (1<<5),
LSR_TEMT = (1<<6),
};
enum {
MSR_DCTS = (1<<0),
MSR_DDSR = (1<<1),
MSR_TERI = (1<<2),
MSR_DDCD = (1<<3),
MSR_CTS = (1<<4),
MSR_DSR = (1<<5),
MSR_RI = (1<<6),
MSR_DCD = (1<<7),
};
#define TYPE_LM32_UART "lm32-uart"
OBJECT_DECLARE_SIMPLE_TYPE(LM32UartState, LM32_UART)
struct LM32UartState {
SysBusDevice parent_obj;
MemoryRegion iomem;
CharBackend chr;
qemu_irq irq;
uint32_t regs[R_MAX];
};
static void uart_update_irq(LM32UartState *s)
{
unsigned int irq;
if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
&& (s->regs[R_IER] & IER_RLSI)) {
irq = 1;
s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
} else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
irq = 1;
s->regs[R_IIR] = IIR_ID1;
} else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
irq = 1;
s->regs[R_IIR] = IIR_ID0;
} else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
irq = 1;
s->regs[R_IIR] = 0;
} else {
irq = 0;
s->regs[R_IIR] = IIR_STAT;
}
trace_lm32_uart_irq_state(irq);
qemu_set_irq(s->irq, irq);
}
static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
LM32UartState *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr) {
case R_RXTX:
r = s->regs[R_RXTX];
s->regs[R_LSR] &= ~LSR_DR;
uart_update_irq(s);
qemu_chr_fe_accept_input(&s->chr);
break;
case R_IIR:
case R_LSR:
case R_MSR:
r = s->regs[addr];
break;
case R_IER:
case R_LCR:
case R_MCR:
case R_DIV:
error_report("lm32_uart: read access to write only register 0x"
TARGET_FMT_plx, addr << 2);
break;
default:
error_report("lm32_uart: read access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
trace_lm32_uart_memory_read(addr << 2, r);
return r;
}
static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
unsigned char ch = value;
trace_lm32_uart_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_RXTX:
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case R_IER:
case R_LCR:
case R_MCR:
case R_DIV:
s->regs[addr] = value;
break;
case R_IIR:
case R_LSR:
case R_MSR:
error_report("lm32_uart: write access to read only register 0x"
TARGET_FMT_plx, addr << 2);
break;
default:
error_report("lm32_uart: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
uart_update_irq(s);
}
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
LM32UartState *s = opaque;
if (s->regs[R_LSR] & LSR_DR) {
s->regs[R_LSR] |= LSR_OE;
}
s->regs[R_LSR] |= LSR_DR;
s->regs[R_RXTX] = *buf;
uart_update_irq(s);
}
static int uart_can_rx(void *opaque)
{
LM32UartState *s = opaque;
return !(s->regs[R_LSR] & LSR_DR);
}
static void uart_event(void *opaque, QEMUChrEvent event)
{
}
static void uart_reset(DeviceState *d)
{
LM32UartState *s = LM32_UART(d);
int i;
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
/* defaults */
s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
}
static void lm32_uart_init(Object *obj)
{
LM32UartState *s = LM32_UART(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, obj, &uart_ops, s,
"uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
}
static void lm32_uart_realize(DeviceState *dev, Error **errp)
{
LM32UartState *s = LM32_UART(dev);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, NULL, s, NULL, true);
}
static const VMStateDescription vmstate_lm32_uart = {
.name = "lm32-uart",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static Property lm32_uart_properties[] = {
DEFINE_PROP_CHR("chardev", LM32UartState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void lm32_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = uart_reset;
dc->vmsd = &vmstate_lm32_uart;
device_class_set_props(dc, lm32_uart_properties);
dc->realize = lm32_uart_realize;
}
static const TypeInfo lm32_uart_info = {
.name = TYPE_LM32_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32UartState),
.instance_init = lm32_uart_init,
.class_init = lm32_uart_class_init,
};
static void lm32_uart_register_types(void)
{
type_register_static(&lm32_uart_info);
}
type_init(lm32_uart_register_types)

3
hw/char/meson.build
View file

@ -8,9 +8,6 @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_serial.c'))
softmmu_ss.add(when: 'CONFIG_IPACK', if_true: files('ipoctal232.c'))
softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('parallel-isa.c'))
softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugcon.c'))
softmmu_ss.add(when: 'CONFIG_LM32_DEVICES', if_true: files('lm32_juart.c'))
softmmu_ss.add(when: 'CONFIG_LM32_DEVICES', if_true: files('lm32_uart.c'))
softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-uart.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_uart.c'))
softmmu_ss.add(when: 'CONFIG_PARALLEL', if_true: files('parallel.c'))
softmmu_ss.add(when: 'CONFIG_PL011', if_true: files('pl011.c'))

258
hw/char/milkymist-uart.c
View file

@ -1,258 +0,0 @@
/*
* QEMU model of the Milkymist UART block.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*
* Specification available at:
* http://milkymist.walle.cc/socdoc/uart.pdf
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "chardev/char-fe.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
R_RXTX = 0,
R_DIV,
R_STAT,
R_CTRL,
R_DBG,
R_MAX
};
enum {
STAT_THRE = (1<<0),
STAT_RX_EVT = (1<<1),
STAT_TX_EVT = (1<<2),
};
enum {
CTRL_RX_IRQ_EN = (1<<0),
CTRL_TX_IRQ_EN = (1<<1),
CTRL_THRU_EN = (1<<2),
};
enum {
DBG_BREAK_EN = (1<<0),
};
#define TYPE_MILKYMIST_UART "milkymist-uart"
OBJECT_DECLARE_SIMPLE_TYPE(MilkymistUartState, MILKYMIST_UART)
struct MilkymistUartState {
SysBusDevice parent_obj;
MemoryRegion regs_region;
CharBackend chr;
qemu_irq irq;
uint32_t regs[R_MAX];
};
static void uart_update_irq(MilkymistUartState *s)
{
int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
trace_milkymist_uart_raise_irq();
qemu_irq_raise(s->irq);
} else {
trace_milkymist_uart_lower_irq();
qemu_irq_lower(s->irq);
}
}
static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistUartState *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr) {
case R_RXTX:
r = s->regs[addr];
break;
case R_DIV:
case R_STAT:
case R_CTRL:
case R_DBG:
r = s->regs[addr];
break;
default:
error_report("milkymist_uart: read access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
trace_milkymist_uart_memory_read(addr << 2, r);
return r;
}
static void uart_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistUartState *s = opaque;
unsigned char ch = value;
trace_milkymist_uart_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_RXTX:
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[R_STAT] |= STAT_TX_EVT;
break;
case R_DIV:
case R_CTRL:
case R_DBG:
s->regs[addr] = value;
break;
case R_STAT:
/* write one to clear bits */
s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
qemu_chr_fe_accept_input(&s->chr);
break;
default:
error_report("milkymist_uart: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
uart_update_irq(s);
}
static const MemoryRegionOps uart_mmio_ops = {
.read = uart_read,
.write = uart_write,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
MilkymistUartState *s = opaque;
assert(!(s->regs[R_STAT] & STAT_RX_EVT));
s->regs[R_STAT] |= STAT_RX_EVT;
s->regs[R_RXTX] = *buf;
uart_update_irq(s);
}
static int uart_can_rx(void *opaque)
{
MilkymistUartState *s = opaque;
return !(s->regs[R_STAT] & STAT_RX_EVT);
}
static void uart_event(void *opaque, QEMUChrEvent event)
{
}
static void milkymist_uart_reset(DeviceState *d)
{
MilkymistUartState *s = MILKYMIST_UART(d);
int i;
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
/* THRE is always set */
s->regs[R_STAT] = STAT_THRE;
}
static void milkymist_uart_realize(DeviceState *dev, Error **errp)
{
MilkymistUartState *s = MILKYMIST_UART(dev);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, NULL, s, NULL, true);
}
static void milkymist_uart_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MilkymistUartState *s = MILKYMIST_UART(obj);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(sbd, &s->regs_region);
}
static const VMStateDescription vmstate_milkymist_uart = {
.name = "milkymist-uart",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static Property milkymist_uart_properties[] = {
DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void milkymist_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = milkymist_uart_realize;
dc->reset = milkymist_uart_reset;
dc->vmsd = &vmstate_milkymist_uart;
device_class_set_props(dc, milkymist_uart_properties);
}
static const TypeInfo milkymist_uart_info = {
.name = TYPE_MILKYMIST_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistUartState),
.instance_init = milkymist_uart_init,
.class_init = milkymist_uart_class_init,
};
static void milkymist_uart_register_types(void)
{
type_register_static(&milkymist_uart_info);
}
type_init(milkymist_uart_register_types)

17
hw/char/trace-events
View file

@ -35,23 +35,6 @@ grlib_apbuart_event(int event) "event:%d"
grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64
# lm32_juart.c
lm32_juart_get_jtx(uint32_t value) "jtx 0x%08x"
lm32_juart_set_jtx(uint32_t value) "jtx 0x%08x"
lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x"
lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x"
# lm32_uart.c
lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
lm32_uart_irq_state(int level) "irq state %d"
# milkymist-uart.c
milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
milkymist_uart_raise_irq(void) "Raise IRQ"
milkymist_uart_lower_irq(void) "Lower IRQ"
# escc.c
escc_put_queue(char channel, int b) "channel %c put: 0x%02x"
escc_get_queue(char channel, int val) "channel %c get 0x%02x"