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target-arm queue:

Browse source 
* hw/core/clock: allow clock_propagate on child clocks
  * hvf: arm: Remove unused PL1_WRITE_MASK define
  * target/arm: Restrict translation disabled alignment check to VMSA
  * docs/system/arm/emulation.rst: Add missing implemented features
  * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
  * tests/avocado: update sunxi kernel from armbian to 6.6.16
  * target/arm: Make new CPUs default to 1GHz generic timer
  * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  * hw/arm: Add DM163 display to B-L475E-IOT01A board
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 =vAf/
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Merge tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/core/clock: allow clock_propagate on child clocks
 * hvf: arm: Remove unused PL1_WRITE_MASK define
 * target/arm: Restrict translation disabled alignment check to VMSA
 * docs/system/arm/emulation.rst: Add missing implemented features
 * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
 * tests/avocado: update sunxi kernel from armbian to 6.6.16
 * target/arm: Make new CPUs default to 1GHz generic timer
 * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
 * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
 * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
 * hw/arm: Add DM163 display to B-L475E-IOT01A board

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# gpg: Signature made Tue 30 Apr 2024 09:47:51 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
  tests/qtest : Add testcase for DM163
  hw/arm : Connect DM163 to B-L475E-IOT01A
  hw/arm : Create Bl475eMachineState
  hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
  hw/display : Add device DM163
  hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
  hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
  hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
  target/arm: Refactor default generic timer frequency handling
  tests/avocado: update sunxi kernel from armbian to 6.6.16
  target/arm: Enable FEAT_Spec_FPACC for -cpu max
  target/arm: Implement ID_AA64MMFR3_EL1
  target/arm: Enable FEAT_ETS2 for -cpu max
  target/arm: Enable FEAT_CSV2_3 for -cpu max
  docs/system/arm/emulation.rst: Add missing implemented features
  target/arm: Restrict translation disabled alignment check to VMSA
  hvf: arm: Remove PL1_WRITE_MASK
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-04-30 09:58:54 -07:00
commit 9c6c079bc6
33 changed files with 986 additions and 123 deletions
Download patch file Download diff file Expand all files Collapse all files

194
tests/qtest/dm163-test.c Normal file
View file

@ -0,0 +1,194 @@
/*
* QTest testcase for DM163
*
* Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
* Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "libqtest.h"
enum DM163_INPUTS {
SIN = 8,
DCK = 9,
RST_B = 10,
LAT_B = 11,
SELBK = 12,
EN_B = 13
};
#define DEVICE_NAME "/machine/dm163"
#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \
value)
#define GPIO_PULSE(name) \
do { \
GPIO_OUT(name, 1); \
GPIO_OUT(name, 0); \
} while (0)
static void rise_gpio_pin_dck(QTestState *qts)
{
/* Configure output mode for pin PB1 */
qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
/* Write 1 in ODR for PB1 */
qtest_writel(qts, 0x48000414, 0x00000002);
}
static void lower_gpio_pin_dck(QTestState *qts)
{
/* Configure output mode for pin PB1 */
qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
/* Write 0 in ODR for PB1 */
qtest_writel(qts, 0x48000414, 0x00000000);
}
static void rise_gpio_pin_selbk(QTestState *qts)
{
/* Configure output mode for pin PC5 */
qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
/* Write 1 in ODR for PC5 */
qtest_writel(qts, 0x48000814, 0x00000020);
}
static void lower_gpio_pin_selbk(QTestState *qts)
{
/* Configure output mode for pin PC5 */
qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
/* Write 0 in ODR for PC5 */
qtest_writel(qts, 0x48000814, 0x00000000);
}
static void rise_gpio_pin_lat_b(QTestState *qts)
{
/* Configure output mode for pin PC4 */
qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
/* Write 1 in ODR for PC4 */
qtest_writel(qts, 0x48000814, 0x00000010);
}
static void lower_gpio_pin_lat_b(QTestState *qts)
{
/* Configure output mode for pin PC4 */
qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
/* Write 0 in ODR for PC4 */
qtest_writel(qts, 0x48000814, 0x00000000);
}
static void rise_gpio_pin_rst_b(QTestState *qts)
{
/* Configure output mode for pin PC3 */
qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
/* Write 1 in ODR for PC3 */
qtest_writel(qts, 0x48000814, 0x00000008);
}
static void lower_gpio_pin_rst_b(QTestState *qts)
{
/* Configure output mode for pin PC3 */
qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
/* Write 0 in ODR for PC3 */
qtest_writel(qts, 0x48000814, 0x00000000);
}
static void rise_gpio_pin_sin(QTestState *qts)
{
/* Configure output mode for pin PA4 */
qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
/* Write 1 in ODR for PA4 */
qtest_writel(qts, 0x48000014, 0x00000010);
}
static void lower_gpio_pin_sin(QTestState *qts)
{
/* Configure output mode for pin PA4 */
qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
/* Write 0 in ODR for PA4 */
qtest_writel(qts, 0x48000014, 0x00000000);
}
static void test_dm163_bank(const void *opaque)
{
const unsigned bank = (uintptr_t) opaque;
const int width = bank ? 192 : 144;
QTestState *qts = qtest_initf("-M b-l475e-iot01a");
qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
GPIO_OUT(RST_B, 1);
GPIO_OUT(EN_B, 0);
GPIO_OUT(DCK, 0);
GPIO_OUT(SELBK, bank);
GPIO_OUT(LAT_B, 1);
/* Fill bank with zeroes */
GPIO_OUT(SIN, 0);
for (int i = 0; i < width; i++) {
GPIO_PULSE(DCK);
}
/* Fill bank with ones, check that we get the previous zeroes */
GPIO_OUT(SIN, 1);
for (int i = 0; i < width; i++) {
GPIO_PULSE(DCK);
g_assert(!qtest_get_irq(qts, 0));
}
/* Pulse one more bit in the bank, check that we get a one */
GPIO_PULSE(DCK);
g_assert(qtest_get_irq(qts, 0));
qtest_quit(qts);
}
static void test_dm163_gpio_connection(void)
{
QTestState *qts = qtest_init("-M b-l475e-iot01a");
qtest_irq_intercept_in(qts, DEVICE_NAME);
g_assert_false(qtest_get_irq(qts, SIN));
g_assert_false(qtest_get_irq(qts, DCK));
g_assert_false(qtest_get_irq(qts, RST_B));
g_assert_false(qtest_get_irq(qts, LAT_B));
g_assert_false(qtest_get_irq(qts, SELBK));
rise_gpio_pin_dck(qts);
g_assert_true(qtest_get_irq(qts, DCK));
lower_gpio_pin_dck(qts);
g_assert_false(qtest_get_irq(qts, DCK));
rise_gpio_pin_lat_b(qts);
g_assert_true(qtest_get_irq(qts, LAT_B));
lower_gpio_pin_lat_b(qts);
g_assert_false(qtest_get_irq(qts, LAT_B));
rise_gpio_pin_selbk(qts);
g_assert_true(qtest_get_irq(qts, SELBK));
lower_gpio_pin_selbk(qts);
g_assert_false(qtest_get_irq(qts, SELBK));
rise_gpio_pin_rst_b(qts);
g_assert_true(qtest_get_irq(qts, RST_B));
lower_gpio_pin_rst_b(qts);
g_assert_false(qtest_get_irq(qts, RST_B));
rise_gpio_pin_sin(qts);
g_assert_true(qtest_get_irq(qts, SIN));
lower_gpio_pin_sin(qts);
g_assert_false(qtest_get_irq(qts, SIN));
g_assert_false(qtest_get_irq(qts, DCK));
g_assert_false(qtest_get_irq(qts, LAT_B));
g_assert_false(qtest_get_irq(qts, SELBK));
g_assert_false(qtest_get_irq(qts, RST_B));
}
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
return g_test_run();
}

2
tests/qtest/meson.build
View file

@ -224,6 +224,8 @@ qtests_arm = \
(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
(config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
['arm-cpu-features',
'boot-serial-test']

13
tests/qtest/stm32l4x5_gpio-test.c
View file

@ -43,6 +43,9 @@
#define OTYPER_PUSH_PULL 0
#define OTYPER_OPEN_DRAIN 1
/* SoC forwards GPIOs to SysCfg */
#define SYSCFG "/machine/soc"
const uint32_t moder_reset[NUM_GPIOS] = {
0xABFFFFFF,
0xFFFFFEBF,
@ -284,7 +287,7 @@ static void test_gpio_output_mode(const void *data)
uint32_t gpio = test_gpio_addr(data);
unsigned int gpio_id = get_gpio_id(gpio);
qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
qtest_irq_intercept_in(global_qtest, SYSCFG);
/* Set a bit in ODR and check nothing happens */
gpio_set_bit(gpio, ODR, pin, 1);
@ -319,7 +322,7 @@ static void test_gpio_input_mode(const void *data)
uint32_t gpio = test_gpio_addr(data);
unsigned int gpio_id = get_gpio_id(gpio);
qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
qtest_irq_intercept_in(global_qtest, SYSCFG);
/* Configure a line as input, raise it, and check that the pin is high */
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@ -348,7 +351,7 @@ static void test_pull_up_pull_down(const void *data)
uint32_t gpio = test_gpio_addr(data);
unsigned int gpio_id = get_gpio_id(gpio);
qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
qtest_irq_intercept_in(global_qtest, SYSCFG);
/* Configure a line as input with pull-up, check the line is set high */
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@ -378,7 +381,7 @@ static void test_push_pull(const void *data)
uint32_t gpio = test_gpio_addr(data);
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
qtest_irq_intercept_in(global_qtest, SYSCFG);
/* Setting a line high externally, configuring it in push-pull output */
/* And checking the pin was disconnected */
@ -425,7 +428,7 @@ static void test_open_drain(const void *data)
uint32_t gpio = test_gpio_addr(data);
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
qtest_irq_intercept_in(global_qtest, SYSCFG);
/* Setting a line high externally, configuring it in open-drain output */
/* And checking the pin was disconnected */

17
tests/qtest/stm32l4x5_syscfg-test.c
View file

@ -1,8 +1,8 @@
/*
* QTest testcase for STM32L4x5_SYSCFG
*
* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@ -25,6 +25,10 @@
#define SYSCFG_SWPR2 0x28
#define INVALID_ADDR 0x2C
/* SoC forwards GPIOs to SysCfg */
#define SYSCFG "/machine/soc"
#define EXTI "/machine/soc/exti"
static void syscfg_writel(unsigned int offset, uint32_t value)
{
writel(SYSCFG_BASE_ADDR + offset, value);
@ -37,8 +41,7 @@ static uint32_t syscfg_readl(unsigned int offset)
static void syscfg_set_irq(int num, int level)
{
qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
NULL, num, level);
qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
}
static void system_reset(void)
@ -197,7 +200,7 @@ static void test_interrupt(void)
* Test that GPIO rising lines result in an irq
* with the right configuration
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
qtest_irq_intercept_in(global_qtest, EXTI);
/* GPIOA is the default source for EXTI lines 0 to 15 */
@ -230,7 +233,7 @@ static void test_irq_pin_multiplexer(void)
* Test that syscfg irq sets the right exti irq
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
qtest_irq_intercept_in(global_qtest, EXTI);
syscfg_set_irq(0, 1);
@ -257,7 +260,7 @@ static void test_irq_gpio_multiplexer(void)
* Test that an irq is generated only by the right GPIO
*/
qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
qtest_irq_intercept_in(global_qtest, EXTI);
/* GPIOA is the default source for EXTI lines 0 to 15 */