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target-arm queue:

Browse source 
* hw/core/clock: allow clock_propagate on child clocks
  * hvf: arm: Remove unused PL1_WRITE_MASK define
  * target/arm: Restrict translation disabled alignment check to VMSA
  * docs/system/arm/emulation.rst: Add missing implemented features
  * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
  * tests/avocado: update sunxi kernel from armbian to 6.6.16
  * target/arm: Make new CPUs default to 1GHz generic timer
  * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  * hw/arm: Add DM163 display to B-L475E-IOT01A board
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Merge tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/core/clock: allow clock_propagate on child clocks
 * hvf: arm: Remove unused PL1_WRITE_MASK define
 * target/arm: Restrict translation disabled alignment check to VMSA
 * docs/system/arm/emulation.rst: Add missing implemented features
 * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
 * tests/avocado: update sunxi kernel from armbian to 6.6.16
 * target/arm: Make new CPUs default to 1GHz generic timer
 * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
 * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
 * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
 * hw/arm: Add DM163 display to B-L475E-IOT01A board

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# gpg: Signature made Tue 30 Apr 2024 09:47:51 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
  tests/qtest : Add testcase for DM163
  hw/arm : Connect DM163 to B-L475E-IOT01A
  hw/arm : Create Bl475eMachineState
  hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
  hw/display : Add device DM163
  hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
  hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
  hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
  target/arm: Refactor default generic timer frequency handling
  tests/avocado: update sunxi kernel from armbian to 6.6.16
  target/arm: Enable FEAT_Spec_FPACC for -cpu max
  target/arm: Implement ID_AA64MMFR3_EL1
  target/arm: Enable FEAT_ETS2 for -cpu max
  target/arm: Enable FEAT_CSV2_3 for -cpu max
  docs/system/arm/emulation.rst: Add missing implemented features
  target/arm: Restrict translation disabled alignment check to VMSA
  hvf: arm: Remove PL1_WRITE_MASK
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-04-30 09:58:54 -07:00
commit 9c6c079bc6
33 changed files with 986 additions and 123 deletions
Download patch file Download diff file Expand all files Collapse all files

59
include/hw/display/dm163.h Normal file
View file

@ -0,0 +1,59 @@
/*
* QEMU DM163 8x3-channel constant current led driver
* driving columns of associated 8x8 RGB matrix.
*
* Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
* Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_DISPLAY_DM163_H
#define HW_DISPLAY_DM163_H
#include "qom/object.h"
#include "hw/qdev-core.h"
#define TYPE_DM163 "dm163"
OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
#define RGB_MATRIX_NUM_ROWS 8
#define RGB_MATRIX_NUM_COLS 8
#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
/* The last row is filled with 0 (turned off row) */
#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
typedef struct DM163State {
DeviceState parent_obj;
/* DM163 driver */
uint64_t bank0_shift_register[3];
uint64_t bank1_shift_register[3];
uint16_t latched_outputs[DM163_NUM_LEDS];
uint16_t outputs[DM163_NUM_LEDS];
qemu_irq sout;
uint8_t sin;
uint8_t dck;
uint8_t rst_b;
uint8_t lat_b;
uint8_t selbk;
uint8_t en_b;
/* IM120417002 colors shield */
uint8_t activated_rows;
/* 8x8 RGB matrix */
QemuConsole *console;
uint8_t redraw;
/* Rows currently being displayed on the matrix. */
/* The last row is filled with 0 (turned off row) */
uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
uint8_t last_buffer_idx;
uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
/* Used to simulate retinal persistence of rows */
uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
} DM163State;
#endif /* HW_DISPLAY_DM163_H */

3
include/hw/watchdog/sbsa_gwdt.h
View file

@ -55,8 +55,6 @@
#define SBSA_GWDT_RMMIO_SIZE 0x1000
#define SBSA_GWDT_CMMIO_SIZE 0x1000
#define SBSA_TIMER_FREQ 62500000 /* Hz */
typedef struct SBSA_GWDTState {
/* <private> */
SysBusDevice parent_obj;
@ -67,6 +65,7 @@ typedef struct SBSA_GWDTState {
qemu_irq irq;
QEMUTimer *timer;
uint64_t freq;
uint32_t id;
uint32_t wcs;