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tcg-aarch64: Use 32-bit loads for qemu_ld_i32

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The "old" qemu_ld opcode did not specify the size of the result,
and so we had to assume full register width.  With the new opcodes,
we can narrow the result.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-09-02 13:59:47 -07:00 • committed by Richard Henderson
parent de8301e542
commit 9c53889ba3
2 changed files with 18 additions and 14 deletions
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5
tcg/tcg-be-ldst.h
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@ -24,8 +24,9 @@
#define TCG_MAX_QEMU_LDST 640
typedef struct TCGLabelQemuLdst {
bool is_ld:1; /* qemu_ld: true, qemu_st: false */
TCGMemOp opc:4;
bool is_ld; /* qemu_ld: true, qemu_st: false */
TCGMemOp opc;
TCGType type; /* result type of a load */
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
TCGReg datalo_reg; /* reg index for low word to be loaded or stored */