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tcg: Convert divu2 to TCGOutOpDivRem

Browse source 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 18:10:14 -08:00
parent ee1805b9e6
commit 9bf558ed17
17 changed files with 69 additions and 50 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tcg/aarch64/tcg-target.c.inc
View file

@ -2183,6 +2183,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_eqv(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

4
tcg/arm/tcg-target.c.inc
View file

@ -1897,6 +1897,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/i386/tcg-target-has.h
View file

@ -26,7 +26,6 @@
#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
/* optional instructions */
#define TCG_TARGET_HAS_div2_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
@ -43,7 +42,6 @@
#if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_div2_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1

20
tcg/i386/tcg-target.c.inc
View file

@ -2653,6 +2653,18 @@ static const TCGOutOpBinary outop_divu = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_divu2(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a4)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, a4);
}
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_O2_I3(a, d, 0, 1, r),
.out_rr01r = tgen_divu2,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
@ -2859,10 +2871,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
OP_32_64(divu2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
break;
OP_32_64(shl):
/* For small constant 3-operand shift, use LEA. */
if (const_a2 && a0 != a1 && (a2 - 1) < 3) {
@ -3798,10 +3806,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_movcond_i64:
return C_O1_I4(r, r, reT, r, 0);
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
return C_O2_I3(a, d, 0, 1, r);
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
case INDEX_op_muls2_i32:

2
tcg/loongarch64/tcg-target-has.h
View file

@ -12,7 +12,6 @@
/* optional instructions */
#define TCG_TARGET_HAS_negsetcond_i32 0
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 0
@ -29,7 +28,6 @@
/* 64-bit operations */
#define TCG_TARGET_HAS_negsetcond_i64 0
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1

4
tcg/loongarch64/tcg-target.c.inc
View file

@ -1362,6 +1362,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};

4
tcg/mips/tcg-target.c.inc
View file

@ -1758,6 +1758,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};

4
tcg/ppc/tcg-target.c.inc
View file

@ -2988,6 +2988,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_eqv,

2
tcg/riscv/tcg-target-has.h
View file

@ -12,7 +12,6 @@
/* optional instructions */
#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1
@ -28,7 +27,6 @@
#define TCG_TARGET_HAS_negsetcond_i64 1
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1

4
tcg/riscv/tcg-target.c.inc
View file

@ -2025,6 +2025,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_eqv(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/s390x/tcg-target-has.h
View file

@ -29,7 +29,6 @@ extern uint64_t s390_facilities[3];
((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
/* optional instructions */
#define TCG_TARGET_HAS_div2_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
@ -45,7 +44,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_div2_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1

36
tcg/s390x/tcg-target.c.inc
View file

@ -2272,6 +2272,23 @@ static const TCGOutOpBinary outop_divu = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_divu2(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a4)
{
tcg_debug_assert((a1 & 1) == 0);
tcg_debug_assert(a0 == a1 + 1);
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RRE, DLR, a1, a4);
} else {
tcg_out_insn(s, RRE, DLGR, a1, a4);
}
}
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_O2_I3(o, m, 0, 1, r),
.out_rr01r = tgen_divu2,
};
static void tgen_eqv(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -2549,14 +2566,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break;
case INDEX_op_divu2_i32:
tcg_debug_assert(args[0] == args[2]);
tcg_debug_assert(args[1] == args[3]);
tcg_debug_assert((args[1] & 1) == 0);
tcg_debug_assert(args[0] == args[1] + 1);
tcg_out_insn(s, RRE, DLR, args[1], args[4]);
break;
case INDEX_op_shl_i32:
op = RS_SLL;
op2 = RSY_SLLK;
@ -2717,13 +2726,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
break;
case INDEX_op_divu2_i64:
tcg_debug_assert(args[0] == args[2]);
tcg_debug_assert(args[1] == args[3]);
tcg_debug_assert((args[1] & 1) == 0);
tcg_debug_assert(args[0] == args[1] + 1);
tcg_out_insn(s, RRE, DLGR, args[1], args[4]);
break;
case INDEX_op_mulu2_i64:
tcg_debug_assert(args[0] == args[2]);
tcg_debug_assert((args[1] & 1) == 0);
@ -3398,10 +3400,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_movcond_i64:
return C_O1_I4(r, r, rC, rI, r);
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
return C_O2_I3(o, m, 0, 1, r);
case INDEX_op_mulu2_i64:
return C_O2_I2(o, m, 0, r);
case INDEX_op_muls2_i64:

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1389,6 +1389,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rri = tgen_divui,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};

7
tcg/tcg-has.h
View file

@ -14,7 +14,6 @@
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_div_i64 0
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 0
#define TCG_TARGET_HAS_bswap16_i64 0
#define TCG_TARGET_HAS_bswap32_i64 0
@ -33,12 +32,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#endif
#ifndef TCG_TARGET_HAS_div2_i32
#define TCG_TARGET_HAS_div2_i32 0
#endif
#ifndef TCG_TARGET_HAS_div2_i64
#define TCG_TARGET_HAS_div2_i64 0
#endif
#ifndef TCG_TARGET_HAS_rem_i32
#define TCG_TARGET_HAS_rem_i32 0
#endif

8
tcg/tcg-op.c
View file

@ -637,7 +637,7 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_divu, ret, arg1, arg2);
} else if (TCG_TARGET_HAS_div2_i32) {
} else if (tcg_op_supported(INDEX_op_divu2_i32, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, zero, arg2);
@ -657,7 +657,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
tcg_gen_mul_i32(t0, t0, arg2);
tcg_gen_sub_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
} else if (TCG_TARGET_HAS_div2_i32) {
} else if (tcg_op_supported(INDEX_op_divu2_i32, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, zero, arg2);
@ -2005,7 +2005,7 @@ void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_divu, ret, arg1, arg2);
} else if (TCG_TARGET_HAS_div2_i64) {
} else if (tcg_op_supported(INDEX_op_divu2_i64, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, zero, arg2);
@ -2025,7 +2025,7 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
tcg_gen_mul_i64(t0, t0, arg2);
tcg_gen_sub_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
} else if (TCG_TARGET_HAS_div2_i64) {
} else if (tcg_op_supported(INDEX_op_divu2_i64, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, zero, arg2);

8
tcg/tcg.c
View file

@ -1029,6 +1029,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu),
OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2),
OUTOP(INDEX_op_divu2_i32, TCGOutOpDivRem, outop_divu2),
OUTOP(INDEX_op_divu2_i64, TCGOutOpDivRem, outop_divu2),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
@ -2272,8 +2274,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
return TCG_TARGET_HAS_rem_i32;
case INDEX_op_divu2_i32:
return TCG_TARGET_HAS_div2_i32;
case INDEX_op_rotl_i32:
case INDEX_op_rotr_i32:
return TCG_TARGET_HAS_rot_i32;
@ -2331,8 +2331,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
return TCG_TARGET_HAS_rem_i64;
case INDEX_op_divu2_i64:
return TCG_TARGET_HAS_div2_i64;
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
return TCG_TARGET_HAS_rot_i64;
@ -5473,6 +5471,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
break;
case INDEX_op_divs2:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
{
const TCGOutOpDivRem *out =
container_of(all_outop[op->opc], TCGOutOpDivRem, base);

4
tcg/tci/tcg-target.c.inc
View file

@ -676,6 +676,10 @@ static const TCGOutOpBinary outop_divu = {
.out_rrr = tgen_divu,
};
static const TCGOutOpDivRem outop_divu2 = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_eqv(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{