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https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 08:13:54 -06:00
hw/arm/smmuv3: Implement translate callback
This patch implements the IOMMU Memory Region translate() callback. Most of the code relates to the translation configuration decoding and check (STE, CD). Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-10-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger
Peter Maydell
parent
bb981004ea
commit
9bde7f0674
3 changed files with 527 additions and 0 deletions
358
hw/arm/smmuv3.c
358
hw/arm/smmuv3.c
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@ -271,6 +271,361 @@ static void smmuv3_init_regs(SMMUv3State *s)
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s->sid_split = 0;
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}
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static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
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SMMUEventInfo *event)
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{
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int ret;
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trace_smmuv3_get_ste(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(void *)buf, sizeof(*buf));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
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event->type = SMMU_EVT_F_STE_FETCH;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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}
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return 0;
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}
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/* @ssid > 0 not supported yet */
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static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
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CD *buf, SMMUEventInfo *event)
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{
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dma_addr_t addr = STE_CTXPTR(ste);
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int ret;
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trace_smmuv3_get_cd(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(void *)buf, sizeof(*buf));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
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event->type = SMMU_EVT_F_CD_FETCH;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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}
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return 0;
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}
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/* Returns <0 if the caller has no need to continue the translation */
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static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
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STE *ste, SMMUEventInfo *event)
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{
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uint32_t config;
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int ret = -EINVAL;
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if (!STE_VALID(ste)) {
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goto bad_ste;
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}
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config = STE_CONFIG(ste);
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if (STE_CFG_ABORT(config)) {
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cfg->aborted = true; /* abort but don't record any event */
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return ret;
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}
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if (STE_CFG_BYPASS(config)) {
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cfg->bypassed = true;
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return ret;
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}
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if (STE_CFG_S2_ENABLED(config)) {
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qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
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goto bad_ste;
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}
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if (STE_S1CDMAX(ste) != 0) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 does not support multiple context descriptors yet\n");
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goto bad_ste;
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}
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if (STE_S1STALLD(ste)) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 S1 stalling fault model not allowed yet\n");
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goto bad_ste;
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}
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return 0;
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bad_ste:
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event->type = SMMU_EVT_C_BAD_STE;
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return -EINVAL;
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}
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/**
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* smmu_find_ste - Return the stream table entry associated
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* to the sid
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*
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* @s: smmuv3 handle
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* @sid: stream ID
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* @ste: returned stream table entry
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* @event: handle to an event info
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*
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* Supports linear and 2-level stream table
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* Return 0 on success, -EINVAL otherwise
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*/
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static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
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SMMUEventInfo *event)
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{
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dma_addr_t addr;
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int ret;
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trace_smmuv3_find_ste(sid, s->features, s->sid_split);
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/* Check SID range */
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if (sid > (1 << SMMU_IDR1_SIDSIZE)) {
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event->type = SMMU_EVT_C_BAD_STREAMID;
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return -EINVAL;
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}
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if (s->features & SMMU_FEATURE_2LVL_STE) {
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int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
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dma_addr_t strtab_base, l1ptr, l2ptr;
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STEDesc l1std;
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strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK;
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l1_ste_offset = sid >> s->sid_split;
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l2_ste_offset = sid & ((1 << s->sid_split) - 1);
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l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std));
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, l1ptr,
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(uint8_t *)&l1std, sizeof(l1std));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Could not read L1PTR at 0X%"PRIx64"\n", l1ptr);
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event->type = SMMU_EVT_F_STE_FETCH;
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event->u.f_ste_fetch.addr = l1ptr;
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return -EINVAL;
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}
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span = L1STD_SPAN(&l1std);
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if (!span) {
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/* l2ptr is not valid */
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qemu_log_mask(LOG_GUEST_ERROR,
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"invalid sid=%d (L1STD span=0)\n", sid);
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event->type = SMMU_EVT_C_BAD_STREAMID;
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return -EINVAL;
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}
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max_l2_ste = (1 << span) - 1;
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l2ptr = l1std_l2ptr(&l1std);
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trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset,
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l2ptr, l2_ste_offset, max_l2_ste);
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if (l2_ste_offset > max_l2_ste) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"l2_ste_offset=%d > max_l2_ste=%d\n",
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l2_ste_offset, max_l2_ste);
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event->type = SMMU_EVT_C_BAD_STE;
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return -EINVAL;
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}
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addr = l2ptr + l2_ste_offset * sizeof(*ste);
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} else {
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addr = s->strtab_base + sid * sizeof(*ste);
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}
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if (smmu_get_ste(s, addr, ste, event)) {
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return -EINVAL;
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}
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return 0;
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}
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static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
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{
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int ret = -EINVAL;
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int i;
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if (!CD_VALID(cd) || !CD_AARCH64(cd)) {
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goto bad_cd;
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}
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if (!CD_A(cd)) {
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goto bad_cd; /* SMMU_IDR0.TERM_MODEL == 1 */
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}
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if (CD_S(cd)) {
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goto bad_cd; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
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}
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if (CD_HA(cd) || CD_HD(cd)) {
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goto bad_cd; /* HTTU = 0 */
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}
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/* we support only those at the moment */
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cfg->aa64 = true;
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cfg->stage = 1;
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cfg->oas = oas2bits(CD_IPS(cd));
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cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
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cfg->tbi = CD_TBI(cd);
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cfg->asid = CD_ASID(cd);
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trace_smmuv3_decode_cd(cfg->oas);
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/* decode data dependent on TT */
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for (i = 0; i <= 1; i++) {
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int tg, tsz;
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SMMUTransTableInfo *tt = &cfg->tt[i];
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cfg->tt[i].disabled = CD_EPD(cd, i);
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if (cfg->tt[i].disabled) {
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continue;
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}
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tsz = CD_TSZ(cd, i);
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if (tsz < 16 || tsz > 39) {
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goto bad_cd;
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}
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tg = CD_TG(cd, i);
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tt->granule_sz = tg2granule(tg, i);
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if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) {
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goto bad_cd;
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}
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tt->tsz = tsz;
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tt->ttb = CD_TTB(cd, i);
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if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) {
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goto bad_cd;
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}
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trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz);
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}
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event->record_trans_faults = CD_R(cd);
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return 0;
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bad_cd:
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event->type = SMMU_EVT_C_BAD_CD;
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return ret;
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}
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/**
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* smmuv3_decode_config - Prepare the translation configuration
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* for the @mr iommu region
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* @mr: iommu memory region the translation config must be prepared for
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* @cfg: output translation configuration which is populated through
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* the different configuration decoding steps
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* @event: must be zero'ed by the caller
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*
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* return < 0 if the translation needs to be aborted (@event is filled
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* accordingly). Return 0 otherwise.
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*/
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static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
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SMMUEventInfo *event)
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{
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SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
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uint32_t sid = smmu_get_sid(sdev);
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SMMUv3State *s = sdev->smmu;
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int ret = -EINVAL;
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STE ste;
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CD cd;
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if (smmu_find_ste(s, sid, &ste, event)) {
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return ret;
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}
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if (decode_ste(s, cfg, &ste, event)) {
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return ret;
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}
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if (smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event)) {
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return ret;
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}
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return decode_cd(cfg, &cd, event);
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}
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static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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IOMMUAccessFlags flag)
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{
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SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
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SMMUv3State *s = sdev->smmu;
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uint32_t sid = smmu_get_sid(sdev);
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SMMUEventInfo event = {.type = SMMU_EVT_OK, .sid = sid};
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SMMUPTWEventInfo ptw_info = {};
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SMMUTransCfg cfg = {};
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IOMMUTLBEntry entry = {
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.target_as = &address_space_memory,
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.iova = addr,
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.translated_addr = addr,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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int ret = 0;
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if (!smmu_enabled(s)) {
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goto out;
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}
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ret = smmuv3_decode_config(mr, &cfg, &event);
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if (ret) {
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goto out;
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}
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if (cfg.aborted) {
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goto out;
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}
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ret = smmu_ptw(&cfg, addr, flag, &entry, &ptw_info);
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if (ret) {
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switch (ptw_info.type) {
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case SMMU_PTW_ERR_WALK_EABT:
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event.type = SMMU_EVT_F_WALK_EABT;
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event.u.f_walk_eabt.addr = addr;
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event.u.f_walk_eabt.rnw = flag & 0x1;
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event.u.f_walk_eabt.class = 0x1;
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event.u.f_walk_eabt.addr2 = ptw_info.addr;
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break;
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case SMMU_PTW_ERR_TRANSLATION:
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_TRANSLATION;
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event.u.f_translation.addr = addr;
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event.u.f_translation.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ADDR_SIZE:
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_ADDR_SIZE;
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event.u.f_addr_size.addr = addr;
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event.u.f_addr_size.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ACCESS:
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_ACCESS;
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event.u.f_access.addr = addr;
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event.u.f_access.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_PERMISSION:
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_PERMISSION;
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event.u.f_permission.addr = addr;
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event.u.f_permission.rnw = flag & 0x1;
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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out:
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if (ret) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s translation failed for iova=0x%"PRIx64"(%d)\n",
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mr->parent_obj.name, addr, ret);
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entry.perm = IOMMU_NONE;
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smmuv3_record_event(s, &event);
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} else if (!cfg.aborted) {
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entry.perm = flag;
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trace_smmuv3_translate(mr->parent_obj.name, sid, addr,
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entry.translated_addr, entry.perm);
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}
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return entry;
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}
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static int smmuv3_cmdq_consume(SMMUv3State *s)
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{
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SMMUCmdError cmd_error = SMMU_CERROR_NONE;
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@ -795,6 +1150,9 @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
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static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
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void *data)
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{
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IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
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imrc->translate = smmuv3_translate;
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}
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static const TypeInfo smmuv3_type_info = {
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