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target/sh4: Populate CPUClass.mmu_index

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 10:55:40 +10:00
parent 4ef80b271f
commit 9ba49d7222
2 changed files with 22 additions and 10 deletions
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16
target/sh4/cpu.c
View file

@ -89,6 +89,21 @@ static bool superh_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD; return cs->interrupt_request & CPU_INTERRUPT_HARD;
} }
int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUSH4State *env = cpu_env(cs);
/*
* The instruction in a RTE delay slot is fetched in privileged mode,
* but executed in user mode.
*/
if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
return 0;
} else {
return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
}
}
static void superh_cpu_reset_hold(Object *obj) static void superh_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(obj); CPUState *s = CPU(obj);
@ -266,6 +281,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name; cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work; cc->has_work = superh_cpu_has_work;
cc->mmu_index = sh4_cpu_mmu_index;
cc->dump_state = superh_cpu_dump_state; cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc; cc->set_pc = superh_cpu_set_pc;
cc->get_pc = superh_cpu_get_pc; cc->get_pc = superh_cpu_get_pc;

16
target/sh4/cpu.h
View file

@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env);
/* MMU modes definitions */ /* MMU modes definitions */
#define MMU_USER_IDX 1 #define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
{
/* The instruction in a RTE delay slot is fetched in privileged
mode, but executed in user mode. */
if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
return 0;
} else {
return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
}
}
#include "exec/cpu-all.h" #include "exec/cpu-all.h"
@ -380,6 +370,12 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
} }
int sh4_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch)
{
return sh4_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags) uint64_t *cs_base, uint32_t *flags)
{ {