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hw/other: spelling fixes

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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:32:24 +03:00
parent 6eedbb5b0c
commit 9b4b4e510b
48 changed files with 85 additions and 85 deletions
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6
hw/ssi/xilinx_spips.c
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@ -163,7 +163,7 @@
FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
/* Poll timeout not implemented */
FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
/* QEMU doesnt care about any of these last three */
/* QEMU doesn't care about any of these last three */
FIELD(GQSPI_CNFG, BR, 3, 3)
FIELD(GQSPI_CNFG, CPH, 2, 1)
FIELD(GQSPI_CNFG, CPL, 1, 1)
@ -469,7 +469,7 @@ static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
/* immedate transfer */
/* immediate transfer */
if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
s->regs[R_GQSPI_DATA_STS] = 1;
@ -768,7 +768,7 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
*/
while (s->regs[R_TRANSFER_SIZE] &&
s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
/* endianess just doesn't matter when zero pumping */
/* endianness just doesn't matter when zero pumping */
tx_data_bytes(&s->tx_fifo, 0, 4, false);
s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
s->regs[R_TRANSFER_SIZE] -= 4;