motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-08 10:13:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/other: spelling fixes

Browse source 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:32:24 +03:00
parent 6eedbb5b0c
commit 9b4b4e510b
48 changed files with 85 additions and 85 deletions
Download patch file Download diff file Expand all files Collapse all files

26
hw/sh4/sh7750_regs.h
View file

@ -113,7 +113,7 @@
#define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS)
#define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS)
/* TLB exeption address register - TEA */
/* TLB exception address register - TEA */
#define SH7750_TEA_REGOFS 0x00000c /* offset */
#define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS)
#define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS)
@ -183,19 +183,19 @@
#define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */
#define SH7750_TRA_IMM_S 2
/* Exeption event register - EXPEVT */
/* Exception event register - EXPEVT */
#define SH7750_EXPEVT_REGOFS 0x000024
#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */
#define SH7750_EXPEVT_EX 0x00000fff /* Exception code */
#define SH7750_EXPEVT_EX_S 0
/* Interrupt event register */
#define SH7750_INTEVT_REGOFS 0x000028
#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
#define SH7750_INTEVT_EX 0x00000fff /* Exception code */
#define SH7750_INTEVT_EX_S 0
/*
@ -1274,15 +1274,15 @@
/*
* User Break Controller registers
*/
#define SH7750_BARA 0x200000 /* Break address regiser A */
#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */
#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */
#define SH7750_BARB 0x20000c /* Break address regiser B */
#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */
#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */
#define SH7750_BASRB 0x000018 /* Break ASID regiser B */
#define SH7750_BDRB 0x200018 /* Break data regiser B */
#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */
#define SH7750_BARA 0x200000 /* Break address register A */
#define SH7750_BAMRA 0x200004 /* Break address mask register A */
#define SH7750_BBRA 0x200008 /* Break bus cycle register A */
#define SH7750_BARB 0x20000c /* Break address register B */
#define SH7750_BAMRB 0x200010 /* Break address mask register B */
#define SH7750_BBRB 0x200014 /* Break bus cycle register B */
#define SH7750_BASRB 0x000018 /* Break ASID register B */
#define SH7750_BDRB 0x200018 /* Break data register B */
#define SH7750_BDMRB 0x20001c /* Break data mask register B */
#define SH7750_BRCR 0x200020 /* Break control register */
#define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */