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target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Helpers that return a pointer into env->vfp.regs so that we isolate the logic of how to index the regs array for different cpu modes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180119045438.28582-7-richard.henderson@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9 changed files with 96 additions and 74 deletions
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@ -164,15 +164,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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if (flags & CPU_DUMP_FPU) {
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int numvfpregs = 32;
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for (i = 0; i < numvfpregs; i += 2) {
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uint64_t vlo = env->vfp.regs[i * 2];
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uint64_t vhi = env->vfp.regs[(i * 2) + 1];
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cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
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i, vhi, vlo);
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vlo = env->vfp.regs[(i + 1) * 2];
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vhi = env->vfp.regs[((i + 1) * 2) + 1];
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cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
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i + 1, vhi, vlo);
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for (i = 0; i < numvfpregs; i++) {
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uint64_t *q = aa64_vfp_qreg(env, i);
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uint64_t vlo = q[0];
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uint64_t vhi = q[1];
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cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c",
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i, vhi, vlo, (i & 1 ? '\n' : ' '));
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}
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cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
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vfp_get_fpcr(env), vfp_get_fpsr(env));
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@ -558,19 +555,13 @@ static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
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*/
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static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)
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{
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int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
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#ifdef HOST_WORDS_BIGENDIAN
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offs += (8 - (1 << size));
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#endif
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assert_fp_access_checked(s);
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return offs;
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return vec_reg_offset(s, regno, 0, size);
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}
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/* Offset of the high half of the 128 bit vector Qn */
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static inline int fp_reg_hi_offset(DisasContext *s, int regno)
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{
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assert_fp_access_checked(s);
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return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
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return vec_reg_offset(s, regno, 1, MO_64);
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}
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/* Convenience accessors for reading and writing single and double
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