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target-or32: Add timer support

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Add OpenRISC timer support.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jia Liu 2012-07-20 15:50:47 +08:00 • committed by Blue Swirl
parent dd29c7fb01
commit 99f575edcc
3 changed files with 124 additions and 1 deletions
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22
target-openrisc/cpu.h
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@ -220,6 +220,22 @@ enum {
OPENRISC_FEATURE_OV64S = (1 << 9),
};
/* Tick Timer Mode Register */
enum {
TTMR_TP = (0xfffffff),
TTMR_IP = (1 << 28),
TTMR_IE = (1 << 29),
TTMR_M = (3 << 30),
};
/* Timer Mode */
enum {
TIMER_NONE = (0 << 30),
TIMER_INTR = (1 << 30),
TIMER_SHOT = (2 << 30),
TIMER_CONT = (3 << 30),
};
/* TLB size */
enum {
DTLB_WAYS = 1,
@ -358,6 +374,12 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
/* hw/openrisc_pic.c */
void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
target_phys_addr_t *physical,