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Get rid of _t suffix

Browse source 
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
malc 2009-10-01 22:20:47 +04:00
parent bc6291a1b9
commit 99a0949b72
316 changed files with 3325 additions and 3332 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/an5206.c
View file

@ -29,7 +29,7 @@ void irq_info(Monitor *mon)
/* Board init. */
static void an5206_init(ram_addr_t ram_size,
static void an5206_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -37,7 +37,7 @@ static void an5206_init(ram_addr_t ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
a_target_phys_addr entry;
if (!cpu_model)
cpu_model = "m5206";

26
hw/apb_pci.c
View file

@ -39,7 +39,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define APB_DPRINTF(fmt, ...)
#endif
typedef target_phys_addr_t pci_addr_t;
typedef a_target_phys_addr a_pci_addr;
#include "pci_host.h"
typedef struct APBState {
@ -47,7 +47,7 @@ typedef struct APBState {
PCIHostState host_state;
} APBState;
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
APBState *s = opaque;
@ -61,7 +61,7 @@ static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
}
static uint32_t pci_apb_config_readl (void *opaque,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
APBState *s = opaque;
uint32_t val;
@ -87,7 +87,7 @@ static CPUReadMemoryFunc * const pci_apb_config_read[] = {
&pci_apb_config_readl,
};
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
static void apb_config_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
//PCIBus *s = opaque;
@ -105,7 +105,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
}
static uint32_t apb_config_readl (void *opaque,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
//PCIBus *s = opaque;
uint32_t val;
@ -148,25 +148,25 @@ static CPUReadMemoryFunc * const pci_apb_read[] = {
&pci_host_data_readl,
};
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -174,7 +174,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -182,7 +182,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -226,8 +226,8 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
PCIBus *pci_apb_init(a_target_phys_addr special_base,
a_target_phys_addr mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;

14
hw/apic.c
View file

@ -661,25 +661,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readb(void *opaque, a_target_phys_addr addr)
{
return 0;
}
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readw(void *opaque, a_target_phys_addr addr)
{
return 0;
}
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
}
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
}
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
{
CPUState *env;
APICState *s;
@ -760,7 +760,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static void apic_send_msi(target_phys_addr_t addr, uint32 data)
static void apic_send_msi(a_target_phys_addr addr, uint32 data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@ -771,7 +771,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32 data)
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
}
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void apic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
CPUState *env;
APICState *s;

4
hw/arm-misc.h
View file

@ -26,8 +26,8 @@ struct arm_boot_info {
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
target_phys_addr_t loader_start;
target_phys_addr_t smp_loader_start;
a_target_phys_addr loader_start;
a_target_phys_addr smp_loader_start;
int nb_cpus;
int board_id;
int (*atag_board)(struct arm_boot_info *info, void *p);

10
hw/arm_boot.c
View file

@ -61,9 +61,9 @@ static void main_cpu_reset(void *opaque)
} while (0)
static void set_kernel_args(struct arm_boot_info *info,
int initrd_size, target_phys_addr_t base)
int initrd_size, a_target_phys_addr base)
{
target_phys_addr_t p;
a_target_phys_addr p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@ -114,9 +114,9 @@ static void set_kernel_args(struct arm_boot_info *info,
}
static void set_kernel_args_old(struct arm_boot_info *info,
int initrd_size, target_phys_addr_t base)
int initrd_size, a_target_phys_addr base)
{
target_phys_addr_t p;
a_target_phys_addr p;
const char *s;
@ -193,7 +193,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
int n;
int is_linux = 0;
uint64_t elf_entry;
target_phys_addr_t entry;
a_target_phys_addr entry;
int big_endian;
/* Load the kernel. */

12
hw/arm_gic.c
View file

@ -238,7 +238,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
}
}
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readb(void *opaque, a_target_phys_addr offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
@ -348,7 +348,7 @@ bad_reg:
return 0;
}
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@ -356,7 +356,7 @@ static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
return val;
}
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
{
uint32_t val;
#ifdef NVIC
@ -371,7 +371,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
return val;
}
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
static void gic_dist_writeb(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@ -509,14 +509,14 @@ bad_reg:
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
static void gic_dist_writew(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
static void gic_dist_writel(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;

4
hw/arm_sysctl.c
View file

@ -27,7 +27,7 @@ typedef struct {
uint32_t resetlevel;
} arm_sysctl_state;
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@ -104,7 +104,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
}
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
static void arm_sysctl_write(void *opaque, a_target_phys_addr offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;

12
hw/arm_timer.c
View file

@ -42,7 +42,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -84,7 +84,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
ptimer_set_limit(s->timer, limit, reload);
}
static void arm_timer_write(void *opaque, target_phys_addr_t offset,
static void arm_timer_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@ -199,7 +199,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
{
sp804_state *s = (sp804_state *)opaque;
@ -211,7 +211,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
}
}
static void sp804_write(void *opaque, target_phys_addr_t offset,
static void sp804_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
sp804_state *s = (sp804_state *)opaque;
@ -283,7 +283,7 @@ typedef struct {
arm_timer_state *timer[3];
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@ -297,7 +297,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
return arm_timer_read(s->timer[n], offset & 0xff);
}
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
static void icp_pit_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
icp_pit_state *s = (icp_pit_state *)opaque;

12
hw/armv7m.c
View file

@ -26,14 +26,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
}
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
static void bitband_writeb(void *opaque, target_phys_addr_t offset,
static void bitband_writeb(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
uint32_t addr;
@ -49,7 +49,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, &v, 1);
}
static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
{
uint32_t addr;
uint16_t mask;
@ -61,7 +61,7 @@ static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
return (v & mask) != 0;
}
static void bitband_writew(void *opaque, target_phys_addr_t offset,
static void bitband_writew(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
uint32_t addr;
@ -78,7 +78,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
{
uint32_t addr;
uint32_t mask;
@ -90,7 +90,7 @@ static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
return (v & mask) != 0;
}
static void bitband_writel(void *opaque, target_phys_addr_t offset,
static void bitband_writel(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
uint32_t addr;

14
hw/axis_dev88.c
View file

@ -44,7 +44,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
{
struct nand_state_t *s = opaque;
uint32_t r;
@ -59,7 +59,7 @@ static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
}
static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
nand_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct nand_state_t *s = opaque;
int rdy;
@ -168,7 +168,7 @@ static struct gpio_state_t
uint32_t regs[0x5c / 4];
} gpio_state;
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@ -197,7 +197,7 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void gpio_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
@ -250,7 +250,7 @@ static void main_cpu_reset(void *opaque)
}
static
void axisdev88_init (ram_addr_t ram_size,
void axisdev88_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -265,8 +265,8 @@ void axisdev88_init (ram_addr_t ram_size,
int i;
int nand_regs;
int gpio_regs;
ram_addr_t phys_ram;
ram_addr_t phys_intmem;
a_ram_addr phys_ram;
a_ram_addr phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {

2
hw/boards.h
View file

@ -5,7 +5,7 @@
#include "qdev.h"
typedef void QEMUMachineInitFunc(ram_addr_t ram_size,
typedef void QEMUMachineInitFunc(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,

4
hw/bt-hci-csr.c
View file

@ -44,7 +44,7 @@ struct csrhci_s {
QEMUTimer *out_tm;
int64_t baud_delay;
bdaddr_t bd_addr;
a_bdaddr bd_addr;
struct HCIInfo *hci;
};
@ -398,7 +398,7 @@ static void csrhci_reset(struct csrhci_s *s)
/* After a while... (but sooner than 10ms) */
s->modem_state |= CHR_TIOCM_CTS;
memset(&s->bd_addr, 0, sizeof(bdaddr_t));
memset(&s->bd_addr, 0, sizeof(a_bdaddr));
}
static void csrhci_out_tick(void *opaque)

16
hw/bt-hci.c
View file

@ -62,7 +62,7 @@ struct bt_hci_s {
uint32_t role_bmp;
int last_handle;
int connecting;
bdaddr_t awaiting_bdaddr[HCI_HANDLES_MAX];
a_bdaddr awaiting_bdaddr[HCI_HANDLES_MAX];
} lm;
uint8_t event_mask[8];
@ -672,7 +672,7 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle)
}
}
static int bt_hci_connect(struct bt_hci_s *hci, bdaddr_t *bdaddr)
static int bt_hci_connect(struct bt_hci_s *hci, a_bdaddr *bdaddr)
{
struct bt_device_s *slave;
struct bt_link_s link;
@ -706,7 +706,7 @@ static void bt_hci_connection_reject(struct bt_hci_s *hci,
}
static void bt_hci_connection_reject_event(struct bt_hci_s *hci,
bdaddr_t *bdaddr)
a_bdaddr *bdaddr)
{
evt_conn_complete params;
@ -808,7 +808,7 @@ static void bt_hci_conn_accept_timeout(void *opaque)
* that's been cancelled by the host in the meantime and immediately
* try to detach the link and send a Connection Complete. */
static int bt_hci_lmp_connection_ready(struct bt_hci_s *hci,
bdaddr_t *bdaddr)
a_bdaddr *bdaddr)
{
int i;
@ -939,7 +939,7 @@ static void bt_hci_lmp_disconnect_slave(struct bt_link_s *btlink)
&params, EVT_DISCONN_COMPLETE_SIZE);
}
static int bt_hci_name_req(struct bt_hci_s *hci, bdaddr_t *bdaddr)
static int bt_hci_name_req(struct bt_hci_s *hci, a_bdaddr *bdaddr)
{
struct bt_device_s *slave;
evt_remote_name_req_complete params;
@ -1290,7 +1290,7 @@ static inline void bt_hci_event_complete_status(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_conn_cancel(struct bt_hci_s *hci,
uint8_t status, bdaddr_t *bd_addr)
uint8_t status, a_bdaddr *bd_addr)
{
create_conn_cancel_rp params = {
.status = status,
@ -1324,7 +1324,7 @@ static inline void bt_hci_event_encrypt_change(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_name_cancel(struct bt_hci_s *hci,
bdaddr_t *bd_addr)
a_bdaddr *bd_addr)
{
remote_name_req_cancel_rp params = {
.status = HCI_INVALID_PARAMETERS,
@ -2134,7 +2134,7 @@ static int bt_hci_bdaddr_set(struct HCIInfo *info, const uint8_t *bd_addr)
{
struct bt_hci_s *hci = hci_from_info(info);
bacpy(&hci->device.bd_addr, (const bdaddr_t *) bd_addr);
bacpy(&hci->device.bd_addr, (const a_bdaddr *) bd_addr);
return 0;
}

78
hw/bt.h
View file

@ -26,20 +26,20 @@
/* BD Address */
typedef struct {
uint8_t b[6];
} __attribute__((packed)) bdaddr_t;
} __attribute__((packed)) a_bdaddr;
#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
#define BDADDR_ANY (&(a_bdaddr) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(a_bdaddr) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(a_bdaddr) {{0, 0, 0, 0xff, 0xff, 0xff}})
/* Copy, swap, convert BD Address */
static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
static inline int bacmp(const a_bdaddr *ba1, const a_bdaddr *ba2)
{
return memcmp(ba1, ba2, sizeof(bdaddr_t));
return memcmp(ba1, ba2, sizeof(a_bdaddr));
}
static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
static inline void bacpy(a_bdaddr *dst, const a_bdaddr *src)
{
memcpy(dst, src, sizeof(bdaddr_t));
memcpy(dst, src, sizeof(a_bdaddr));
}
#define BAINIT(orig) { .b = { \
@ -71,7 +71,7 @@ struct bt_link_s {
struct bt_device_s {
int lt_addr;
bdaddr_t bd_addr;
a_bdaddr bd_addr;
int mtu;
int setup;
struct bt_scatternet_s *net;
@ -451,7 +451,7 @@ typedef struct {
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) status_bdaddr_rp;
#define STATUS_BDADDR_RP_SIZE 7
@ -471,7 +471,7 @@ typedef struct {
#define OCF_CREATE_CONN 0x0005
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint16_t pkt_type;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
@ -497,33 +497,33 @@ typedef struct {
#define OCF_CREATE_CONN_CANCEL 0x0008
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) create_conn_cancel_cp;
#define CREATE_CONN_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) create_conn_cancel_rp;
#define CREATE_CONN_CANCEL_RP_SIZE 7
#define OCF_ACCEPT_CONN_REQ 0x0009
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t role;
} __attribute__ ((packed)) accept_conn_req_cp;
#define ACCEPT_CONN_REQ_CP_SIZE 7
#define OCF_REJECT_CONN_REQ 0x000A
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_conn_req_cp;
#define REJECT_CONN_REQ_CP_SIZE 7
#define OCF_LINK_KEY_REPLY 0x000B
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t link_key[16];
} __attribute__ ((packed)) link_key_reply_cp;
#define LINK_KEY_REPLY_CP_SIZE 22
@ -532,7 +532,7 @@ typedef struct {
#define OCF_PIN_CODE_REPLY 0x000D
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pin_len;
uint8_t pin_code[16];
} __attribute__ ((packed)) pin_code_reply_cp;
@ -574,7 +574,7 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ 0x0019
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
uint16_t clock_offset;
@ -583,13 +583,13 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_cp;
#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_rp;
#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
@ -646,7 +646,7 @@ typedef struct {
#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint32_t tx_bandwith;
uint32_t rx_bandwith;
uint16_t max_latency;
@ -658,7 +658,7 @@ typedef struct {
#define OCF_REJECT_SYNC_CONN_REQ 0x002A
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_sync_conn_req_cp;
#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
@ -734,7 +734,7 @@ typedef struct {
#define OCF_SWITCH_ROLE 0x000B
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t role;
} __attribute__ ((packed)) switch_role_cp;
#define SWITCH_ROLE_CP_SIZE 7
@ -847,7 +847,7 @@ typedef struct {
#define OCF_READ_STORED_LINK_KEY 0x000D
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t read_all;
} __attribute__ ((packed)) read_stored_link_key_cp;
#define READ_STORED_LINK_KEY_CP_SIZE 7
@ -872,7 +872,7 @@ typedef struct {
#define OCF_DELETE_STORED_LINK_KEY 0x0012
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t delete_all;
} __attribute__ ((packed)) delete_stored_link_key_cp;
#define DELETE_STORED_LINK_KEY_CP_SIZE 7
@ -1238,7 +1238,7 @@ typedef struct {
#define OCF_READ_BD_ADDR 0x0009
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) read_bd_addr_rp;
#define READ_BD_ADDR_RP_SIZE 7
@ -1317,7 +1317,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT 0x02
typedef struct {
uint8_t num_responses;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@ -1330,7 +1330,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t link_type;
uint8_t encr_mode;
} __attribute__ ((packed)) evt_conn_complete;
@ -1338,7 +1338,7 @@ typedef struct {
#define EVT_CONN_REQUEST 0x04
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t dev_class[3];
uint8_t link_type;
} __attribute__ ((packed)) evt_conn_request;
@ -1362,7 +1362,7 @@ typedef struct {
#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
char name[248];
} __attribute__ ((packed)) evt_remote_name_req_complete;
#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
@ -1447,7 +1447,7 @@ typedef struct {
#define EVT_ROLE_CHANGE 0x12
typedef struct {
uint8_t status;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t role;
} __attribute__ ((packed)) evt_role_change;
#define EVT_ROLE_CHANGE_SIZE 8
@ -1480,19 +1480,19 @@ typedef struct {
#define EVT_PIN_CODE_REQ 0x16
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) evt_pin_code_req;
#define EVT_PIN_CODE_REQ_SIZE 6
#define EVT_LINK_KEY_REQ 0x17
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
} __attribute__ ((packed)) evt_link_key_req;
#define EVT_LINK_KEY_REQ_SIZE 6
#define EVT_LINK_KEY_NOTIFY 0x18
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t link_key[16];
uint8_t key_type;
} __attribute__ ((packed)) evt_link_key_notify;
@ -1537,7 +1537,7 @@ typedef struct {
#define EVT_PSCAN_REP_MODE_CHANGE 0x20
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
} __attribute__ ((packed)) evt_pscan_rep_mode_change;
#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
@ -1555,7 +1555,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
typedef struct {
uint8_t num_responses;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
@ -1565,7 +1565,7 @@ typedef struct {
#define INQUIRY_INFO_WITH_RSSI_SIZE 15
typedef struct {
uint8_t num_responses;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@ -1589,7 +1589,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t link_type;
uint8_t trans_interval;
uint8_t retrans_window;
@ -1623,7 +1623,7 @@ typedef struct {
#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
typedef struct {
bdaddr_t bdaddr;
a_bdaddr bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];

50
hw/cirrus_vga.c
View file

@ -1214,7 +1214,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
/* Thinking about changing bank base? First, drop the dirty bitmap information
* on the current location, otherwise we lose this pointer forever */
if (s->vga.lfb_vram_mapped) {
target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
a_target_phys_addr base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
}
s->cirrus_bank_base[bank_index] = offset;
@ -1988,7 +1988,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
*
***************************************/
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
@ -2032,7 +2032,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2045,7 +2045,7 @@ static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
return v;
}
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2062,7 +2062,7 @@ static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
uint32_t mem_value)
{
CirrusVGAState *s = opaque;
@ -2127,7 +2127,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
}
}
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
@ -2138,7 +2138,7 @@ static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_
#endif
}
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cirrus_vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
@ -2341,7 +2341,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
*
***************************************/
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
{
CirrusVGAState *s = opaque;
uint32_t ret;
@ -2369,7 +2369,7 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
return ret;
}
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2382,7 +2382,7 @@ static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
return v;
}
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2399,7 +2399,7 @@ static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2440,7 +2440,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
}
}
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2452,7 +2452,7 @@ static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
#endif
}
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2488,7 +2488,7 @@ static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
***************************************/
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr)
{
uint32_t ret;
@ -2497,7 +2497,7 @@ static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr
return ret;
}
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2510,7 +2510,7 @@ static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr
return v;
}
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2527,7 +2527,7 @@ static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr
return v;
}
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2541,7 +2541,7 @@ static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
}
}
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2553,7 +2553,7 @@ static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
#endif
}
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
static void cirrus_linear_bitblt_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2855,7 +2855,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
*
***************************************/
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
{
CirrusVGAState *s = opaque;
@ -2868,7 +2868,7 @@ static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
}
}
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2881,7 +2881,7 @@ static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
return v;
}
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -2898,7 +2898,7 @@ static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@ -2912,7 +2912,7 @@ static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
}
}
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -2924,7 +2924,7 @@ static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
#endif
}
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
static void cirrus_mmio_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN

4
hw/cs4231.c
View file

@ -64,7 +64,7 @@ static void cs_reset(void *opaque)
s->dregs[25] = CS_VER;
}
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
{
CSState *s = opaque;
uint32_t saddr, ret;
@ -90,7 +90,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
CSState *s = opaque;
uint32_t saddr;

12
hw/cuda.c
View file

@ -250,7 +250,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
{
CUDAState *s = opaque;
uint32_t val;
@ -321,7 +321,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
return val;
}
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cuda_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
CUDAState *s = opaque;
@ -612,20 +612,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void cuda_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
{
}
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void cuda_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
}
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readw (void *opaque, a_target_phys_addr addr)
{
return 0;
}
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
static uint32_t cuda_readl (void *opaque, a_target_phys_addr addr)
{
return 0;
}

4
hw/dma.c
View file

@ -401,7 +401,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@ -423,7 +423,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;

18
hw/dp8393x.c
View file

@ -166,7 +166,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
@ -601,7 +601,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
{
dp8393xState *s = opaque;
int reg;
@ -614,13 +614,13 @@ static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
return read_register(s, reg);
}
static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readb(void *opaque, a_target_phys_addr addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@ -628,7 +628,7 @@ static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@ -642,7 +642,7 @@ static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@ -657,7 +657,7 @@ static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dp8393x_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@ -872,9 +872,9 @@ static void nic_cleanup(VLANClientState *vc)
qemu_free(s);
}
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;

32
hw/ds1225y.c
View file

@ -34,12 +34,12 @@ typedef struct ds1225y_t
QEMUFile *file;
uint8_t *contents;
uint8_t protection;
} ds1225y_t;
} a_ds1225y;
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
{
ds1225y_t *s = opaque;
a_ds1225y *s = opaque;
uint32_t val;
val = s->contents[addr];
@ -50,7 +50,7 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@ -58,7 +58,7 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
return v;
}
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@ -68,9 +68,9 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
return v;
}
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
{
ds1225y_t *s = opaque;
a_ds1225y *s = opaque;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
@ -84,13 +84,13 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
@ -98,9 +98,9 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
{
ds1225y_t *s = opaque;
a_ds1225y *s = opaque;
if (s->protection != 7) {
#ifdef DEBUG_NVRAM
@ -112,13 +112,13 @@ static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint3
nvram_writeb(opaque, addr, val);
}
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writew_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_writel_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
@ -145,13 +145,13 @@ static CPUWriteMemoryFunc * const nvram_write_protected[] = {
};
/* Initialisation routine */
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
void *ds1225y_init(a_target_phys_addr mem_base, const char *filename)
{
ds1225y_t *s;
a_ds1225y *s;
int mem_indexRW, mem_indexRP;
QEMUFile *file;
s = qemu_mallocz(sizeof(ds1225y_t));
s = qemu_mallocz(sizeof(a_ds1225y));
s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
s->protection = 7;

4
hw/dummy_m68k.c
View file

@ -16,7 +16,7 @@
/* Board init. */
static void dummy_m68k_init(ram_addr_t ram_size,
static void dummy_m68k_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -24,7 +24,7 @@ static void dummy_m68k_init(ram_addr_t ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
a_target_phys_addr entry;
if (!cpu_model)
cpu_model = "cfv4e";

18
hw/e1000.c
View file

@ -478,7 +478,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
}
static uint32_t
txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
{
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
@ -495,7 +495,7 @@ txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
static void
start_xmit(E1000State *s)
{
target_phys_addr_t base;
a_target_phys_addr base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
@ -613,7 +613,7 @@ e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
E1000State *s = vc->opaque;
struct e1000_rx_desc desc;
target_phys_addr_t base;
a_target_phys_addr base;
unsigned int n, rdt;
uint32_t rdh_start;
uint16_t vlan_special = 0;
@ -814,7 +814,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@ -832,7 +832,7 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
static void
e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@ -840,7 +840,7 @@ e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
}
static void
e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@ -848,7 +848,7 @@ e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
}
static uint32_t
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@ -866,14 +866,14 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
}
static uint32_t
e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
e1000_mmio_readb(void *opaque, a_target_phys_addr addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xff;
}
static uint32_t
e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
e1000_mmio_readw(void *opaque, a_target_phys_addr addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xffff;

8
hw/eccmemctl.c
View file

@ -133,7 +133,7 @@ typedef struct ECCState {
uint32_t version;
} ECCState;
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
ECCState *s = opaque;
@ -175,7 +175,7 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t ecc_mem_readl(void *opaque, a_target_phys_addr addr)
{
ECCState *s = opaque;
uint32_t ret = 0;
@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
ecc_mem_writel,
};
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
ECCState *s = opaque;
@ -242,7 +242,7 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t ecc_diag_mem_readb(void *opaque, a_target_phys_addr addr)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];

54
hw/eepro100.c
View file

@ -144,7 +144,7 @@ typedef struct {
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
//~ int32_t tx_buf_size1; /* Length of Tx data. */
} eepro100_tx_t;
} a_eepro100_tx;
/* Receive frame descriptor. */
typedef struct {
@ -155,7 +155,7 @@ typedef struct {
uint16_t count;
uint16_t size;
char packet[MAX_ETH_FRAME_SIZE + 4];
} eepro100_rx_t;
} a_eepro100_rx;
typedef struct {
uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
@ -167,7 +167,7 @@ typedef struct {
uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
uint16_t xmt_tco_frames, rcv_tco_frames;
uint32_t complete;
} eepro100_stats_t;
} a_eepro100_stats;
typedef enum {
cu_idle = 0,
@ -175,14 +175,14 @@ typedef enum {
cu_active = 2,
cu_lpq_active = 2,
cu_hqp_active = 3
} cu_state_t;
} a_cu_state;
typedef enum {
ru_idle = 0,
ru_suspended = 1,
ru_no_resources = 2,
ru_ready = 4
} ru_state_t;
} a_ru_state;
typedef struct {
PCIDevice dev;
@ -213,7 +213,7 @@ typedef struct {
uint8_t macaddr[6];
uint32_t statcounter[19];
uint16_t mdimem[32];
eeprom_t *eeprom;
a_eeprom *eeprom;
uint32_t device; /* device variant */
uint32_t pointer;
/* (cu_base + cu_offset) address the next command block in the command block list. */
@ -222,8 +222,8 @@ typedef struct {
/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
uint32_t ru_base; /* RU base address */
uint32_t ru_offset; /* RU address offset */
uint32_t statsaddr; /* pointer to eepro100_stats_t */
eepro100_stats_t statistics; /* statistical counters */
uint32_t statsaddr; /* pointer to a_eepro100_stats */
a_eepro100_stats statistics; /* statistical counters */
#if 0
uint16_t status;
#endif
@ -600,22 +600,22 @@ enum commands {
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
};
static cu_state_t get_cu_state(EEPRO100State * s)
static a_cu_state get_cu_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 6) & 0x03);
}
static void set_cu_state(EEPRO100State * s, cu_state_t state)
static void set_cu_state(EEPRO100State * s, a_cu_state state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
}
static ru_state_t get_ru_state(EEPRO100State * s)
static a_ru_state get_ru_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 2) & 0x0f);
}
static void set_ru_state(EEPRO100State * s, ru_state_t state)
static void set_ru_state(EEPRO100State * s, a_ru_state state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
}
@ -639,7 +639,7 @@ static void dump_statistics(EEPRO100State * s)
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
{
eepro100_tx_t tx;
a_eepro100_tx tx;
uint32_t cb_address;
switch (val) {
case CU_NOP:
@ -915,7 +915,7 @@ static uint16_t eepro100_read_eeprom(EEPRO100State * s)
return val;
}
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val)
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
@ -1099,7 +1099,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
typedef struct {
uint32_t st_sign; /* Self Test Signature */
uint32_t st_result; /* Self Test Results */
} eepro100_selftest_t;
} a_eepro100_selftest;
static uint32_t eepro100_read_port(EEPRO100State * s)
{
@ -1117,7 +1117,7 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val)
break;
case PORT_SELFTEST:
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
eepro100_selftest_t data;
a_eepro100_selftest data;
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
data.st_sign = 0xffffffff;
data.st_result = 0;
@ -1398,42 +1398,42 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
*
****************************************************************************/
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
@ -1541,9 +1541,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
//~ !!!
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
eepro100_rx_t rx;
a_eepro100_rx rx;
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
offsetof(eepro100_rx_t, packet));
offsetof(a_eepro100_rx, packet));
uint16_t rfd_command = le16_to_cpu(rx.command);
uint16_t rfd_size = le16_to_cpu(rx.size);
assert(size <= rfd_size);
@ -1552,9 +1552,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status),
rfd_status);
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size);
/* Early receive interrupt not supported. */
//~ eepro100_er_interrupt(s);
/* Receive CRC Transfer not supported. */
@ -1562,7 +1562,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
/* TODO: check stripping enable bit. */
//~ assert(!(s->configuration[17] & 1));
cpu_physical_memory_write(s->ru_base + s->ru_offset +
offsetof(eepro100_rx_t, packet), buf, size);
offsetof(a_eepro100_rx, packet), buf, size);
s->statistics.rx_good_frames++;
eepro100_fr_interrupt(s);
s->ru_offset = le32_to_cpu(rx.link);

20
hw/eeprom93xx.c
View file

@ -71,7 +71,7 @@ static const char *opstring[] = {
};
#endif
struct _eeprom_t {
struct eeprom {
uint8_t tick;
uint8_t address;
uint8_t command;
@ -93,7 +93,7 @@ static void eeprom_save(QEMUFile *f, void *opaque)
{
/* Save EEPROM data. */
unsigned address;
eeprom_t *eeprom = (eeprom_t *)opaque;
a_eeprom *eeprom = (a_eeprom *)opaque;
qemu_put_byte(f, eeprom->tick);
qemu_put_byte(f, eeprom->address);
@ -116,7 +116,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
{
/* Load EEPROM data from saved data if version and EEPROM size
of data and current EEPROM are identical. */
eeprom_t *eeprom = (eeprom_t *)opaque;
a_eeprom *eeprom = (a_eeprom *)opaque;
int result = -EINVAL;
if (version_id >= OLD_EEPROM_VERSION) {
unsigned address;
@ -150,7 +150,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
return result;
}
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
@ -275,7 +275,7 @@ void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
eeprom->command = command;
}
uint16_t eeprom93xx_read(eeprom_t *eeprom)
uint16_t eeprom93xx_read(a_eeprom *eeprom)
{
/* Return status of pin DO (0 or 1). */
logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo);
@ -292,10 +292,10 @@ void eeprom93xx_reset(eeprom_t *eeprom)
}
#endif
eeprom_t *eeprom93xx_new(uint16_t nwords)
a_eeprom *eeprom93xx_new(uint16_t nwords)
{
/* Add a new EEPROM (with 16, 64 or 256 words). */
eeprom_t *eeprom;
a_eeprom *eeprom;
uint8_t addrbits;
switch (nwords) {
@ -313,7 +313,7 @@ eeprom_t *eeprom93xx_new(uint16_t nwords)
addrbits = 6;
}
eeprom = (eeprom_t *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom = (a_eeprom *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
@ -324,7 +324,7 @@ eeprom_t *eeprom93xx_new(uint16_t nwords)
return eeprom;
}
void eeprom93xx_free(eeprom_t *eeprom)
void eeprom93xx_free(a_eeprom *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
@ -332,7 +332,7 @@ void eeprom93xx_free(eeprom_t *eeprom)
qemu_free(eeprom);
}
uint16_t *eeprom93xx_data(eeprom_t *eeprom)
uint16_t *eeprom93xx_data(a_eeprom *eeprom)
{
/* Get EEPROM data array. */
return &eeprom->contents[0];

12
hw/eeprom93xx.h
View file

@ -20,21 +20,21 @@
#ifndef EEPROM93XX_H
#define EEPROM93XX_H
typedef struct _eeprom_t eeprom_t;
typedef struct eeprom a_eeprom;
/* Create a new EEPROM with (nwords * 2) bytes. */
eeprom_t *eeprom93xx_new(uint16_t nwords);
a_eeprom *eeprom93xx_new(uint16_t nwords);
/* Destroy an existing EEPROM. */
void eeprom93xx_free(eeprom_t *eeprom);
void eeprom93xx_free(a_eeprom *eeprom);
/* Read from the EEPROM. */
uint16_t eeprom93xx_read(eeprom_t *eeprom);
uint16_t eeprom93xx_read(a_eeprom *eeprom);
/* Write to the EEPROM. */
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi);
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi);
/* Get EEPROM data array. */
uint16_t *eeprom93xx_data(eeprom_t *eeprom);
uint16_t *eeprom93xx_data(a_eeprom *eeprom);
#endif /* EEPROM93XX_H */

2
hw/elf_ops.h
View file

@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
target_phys_addr_t orig_addr)
a_target_phys_addr orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym key;

16
hw/escc.c
View file

@ -84,13 +84,13 @@
typedef enum {
chn_a, chn_b,
} chn_id_t;
} e_chn_id;
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
typedef enum {
ser, kbd, mouse,
} chn_type_t;
} e_chn_type;
#define SERIO_QUEUE_SIZE 256
@ -104,8 +104,8 @@ typedef struct ChannelState {
qemu_irq irq;
uint32_t reg;
uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
chn_id_t chn; // this channel, A (base+4) or B (base+0)
chn_type_t type;
e_chn_id chn; // this channel, A (base+4) or B (base+0)
e_chn_type type;
struct ChannelState *otherchn;
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
@ -481,7 +481,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
SerialState *serial = opaque;
ChannelState *s;
@ -578,7 +578,7 @@ static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr)
{
SerialState *serial = opaque;
ChannelState *s;
@ -725,7 +725,7 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id)
}
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@ -890,7 +890,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;

4
hw/escc.h
View file

@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
int disabled, int clock, int it_shift);

6
hw/esp.c
View file

@ -439,7 +439,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
esp_reset(opaque);
}
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
@ -480,7 +480,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
return s->rregs[saddr];
}
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void esp_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
ESPState *s = opaque;
uint32_t saddr;
@ -632,7 +632,7 @@ static const VMStateDescription vmstate_esp = {
}
};
void esp_init(target_phys_addr_t espaddr, int it_shift,
void esp_init(a_target_phys_addr espaddr, int it_shift,
espdma_memory_read_write dma_memory_read,
espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)

8
hw/etraxfs.c
View file

@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
}
static
void bareetraxfs_init (ram_addr_t ram_size,
void bareetraxfs_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -59,9 +59,9 @@ void bareetraxfs_init (ram_addr_t ram_size,
int kernel_size;
DriveInfo *dinfo;
int i;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
ram_addr_t phys_intmem;
a_ram_addr phys_ram;
a_ram_addr phys_flash;
a_ram_addr phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {

2
hw/etraxfs.h
View file

@ -25,4 +25,4 @@
#include "etraxfs_dma.h"
qemu_irq *cris_pic_init_cpu(CPUState *env);
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr);
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr);

22
hw/etraxfs_dma.c
View file

@ -211,7 +211,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
static inline int fs_channel(target_phys_addr_t addr)
static inline int fs_channel(a_target_phys_addr addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@ -220,7 +220,7 @@ static inline int fs_channel(target_phys_addr_t addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -252,7 +252,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@ -269,7 +269,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -283,7 +283,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -295,7 +295,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@ -556,14 +556,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
return 0;
}
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
static uint32_t dma_rinvalid (void *opaque, a_target_phys_addr addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint32_t
dma_readl (void *opaque, target_phys_addr_t addr)
dma_readl (void *opaque, a_target_phys_addr addr)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@ -591,7 +591,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
}
static void
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
dma_winvalid (void *opaque, a_target_phys_addr addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@ -608,7 +608,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
}
static void
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
dma_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@ -739,7 +739,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;

2
hw/etraxfs_dma.h
View file

@ -13,7 +13,7 @@ struct etraxfs_dma_client
} client;
};
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,

6
hw/etraxfs_eth.c
View file

@ -365,7 +365,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
}
static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
static uint32_t eth_readl (void *opaque, a_target_phys_addr addr)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@ -409,7 +409,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct fs_eth *eth = opaque;
@ -564,7 +564,7 @@ static void eth_cleanup(VLANClientState *vc)
qemu_free(eth);
}
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr)
{
struct etraxfs_dma_client *dma = NULL;
struct fs_eth *eth = NULL;

4
hw/etraxfs_pic.c
View file

@ -77,7 +77,7 @@ static void pic_update(struct etrax_pic *fs)
qemu_set_irq(fs->parent_irq, !!vector);
}
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
}
static void
pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct etrax_pic *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));

4
hw/etraxfs_ser.c
View file

@ -65,7 +65,7 @@ static void ser_update_irq(struct etrax_serial *s)
s->regs[RW_ACK_INTR] = 0;
}
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
@ -91,7 +91,7 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
ser_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;

4
hw/etraxfs_timer.c
View file

@ -72,7 +72,7 @@ struct etrax_timer {
uint32_t r_masked_intr;
};
static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
static uint32_t timer_readl (void *opaque, a_target_phys_addr addr)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@ -243,7 +243,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
}
static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct etrax_timer *t = opaque;

344
hw/fdc.c
View file

@ -61,43 +61,43 @@
#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
typedef enum fdisk_type_t {
typedef enum fdisk_type {
FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
FDRIVE_DISK_USER = 0x04, /* User defined geometry */
FDRIVE_DISK_NONE = 0x05, /* No disk */
} fdisk_type_t;
} e_fdisk_type;
typedef enum fdrive_type_t {
typedef enum fdrive_type {
FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
FDRIVE_DRV_NONE = 0x03, /* No drive connected */
} fdrive_type_t;
} e_fdrive_type;
typedef enum fdisk_flags_t {
typedef enum fdisk_flags {
FDISK_DBL_SIDES = 0x01,
} fdisk_flags_t;
} e_fdisk_flags;
typedef struct fdrive_t {
typedef struct fdrive {
BlockDriverState *bs;
/* Drive status */
fdrive_type_t drive;
e_fdrive_type drive;
uint8_t perpendicular; /* 2.88 MB access mode */
/* Position */
uint8_t head;
uint8_t track;
uint8_t sect;
/* Media */
fdisk_flags_t flags;
e_fdisk_flags flags;
uint8_t last_sect; /* Nb sector per track */
uint8_t max_track; /* Nb of tracks */
uint16_t bps; /* Bytes per sector */
uint8_t ro; /* Is read-only */
} fdrive_t;
} a_fdrive;
static void fd_init (fdrive_t *drv, BlockDriverState *bs)
static void fd_init (a_fdrive *drv, BlockDriverState *bs)
{
/* Drive */
drv->bs = bs;
@ -115,7 +115,7 @@ static int _fd_sector (uint8_t head, uint8_t track,
}
/* Returns current position, in sectors, for given drive */
static int fd_sector (fdrive_t *drv)
static int fd_sector (a_fdrive *drv)
{
return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
}
@ -127,7 +127,7 @@ static int fd_sector (fdrive_t *drv)
* returns 3 if sector is invalid
* returns 4 if seek is disabled
*/
static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect,
int enable_seek)
{
uint32_t sector;
@ -169,7 +169,7 @@ static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
}
/* Set drive back to track 0 */
static void fd_recalibrate (fdrive_t *drv)
static void fd_recalibrate (a_fdrive *drv)
{
FLOPPY_DPRINTF("recalibrate\n");
drv->head = 0;
@ -178,16 +178,16 @@ static void fd_recalibrate (fdrive_t *drv)
}
/* Recognize floppy formats */
typedef struct fd_format_t {
fdrive_type_t drive;
fdisk_type_t disk;
typedef struct fd_format {
e_fdrive_type drive;
e_fdisk_type disk;
uint8_t last_sect;
uint8_t max_track;
uint8_t max_head;
const char *str;
} fd_format_t;
} a_fd_format;
static const fd_format_t fd_formats[] = {
static const a_fd_format fd_formats[] = {
/* First entry is default format */
/* 1.44 MB 3"1/2 floppy disks */
{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
@ -235,9 +235,9 @@ static const fd_format_t fd_formats[] = {
};
/* Revalidate a disk drive after a disk change */
static void fd_revalidate (fdrive_t *drv)
static void fd_revalidate (a_fdrive *drv)
{
const fd_format_t *parse;
const a_fd_format *parse;
uint64_t nb_sectors, size;
int i, first_match, match;
int nb_heads, max_track, last_sect, ro;
@ -302,23 +302,23 @@ static void fd_revalidate (fdrive_t *drv)
/********************************************************/
/* Intel 82078 floppy disk controller emulation */
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq);
static void fdctrl_reset_fifo (a_fdctrl *fdctrl);
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len);
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
int dma_pos, int dma_len);
static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0);
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl);
static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl);
static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl);
static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl);
static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl);
static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_data (a_fdctrl *fdctrl);
static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value);
static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl);
enum {
FD_DIR_WRITE = 0,
@ -470,7 +470,7 @@ enum {
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
struct fdctrl_t {
struct fdctrl {
/* Controller's identification */
uint8_t version;
/* HW */
@ -511,23 +511,23 @@ struct fdctrl_t {
int sun4m;
/* Floppy drives */
uint8_t num_floppies;
fdrive_t drives[MAX_FD];
a_fdrive drives[MAX_FD];
int reset_sensei;
};
typedef struct fdctrl_sysbus_t {
typedef struct fdctrl_sysbus {
SysBusDevice busdev;
struct fdctrl_t state;
} fdctrl_sysbus_t;
struct fdctrl state;
} a_fdctrl_sysbus;
typedef struct fdctrl_isabus_t {
typedef struct fdctrl_isabus {
ISADevice busdev;
struct fdctrl_t state;
} fdctrl_isabus_t;
struct fdctrl state;
} a_fdctrl_isabus;
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
fdctrl_t *fdctrl = opaque;
a_fdctrl *fdctrl = opaque;
uint32_t retval;
switch (reg) {
@ -563,7 +563,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
{
fdctrl_t *fdctrl = opaque;
a_fdctrl *fdctrl = opaque;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
@ -595,13 +595,13 @@ static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
fdctrl_write(opaque, reg & 7, value);
}
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
static uint32_t fdctrl_read_mem (void *opaque, a_target_phys_addr reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
static void fdctrl_write_mem (void *opaque,
target_phys_addr_t reg, uint32_t value)
a_target_phys_addr reg, uint32_t value)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
@ -636,23 +636,23 @@ static const VMStateDescription vmstate_fdrive = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT8(head, fdrive_t),
VMSTATE_UINT8(track, fdrive_t),
VMSTATE_UINT8(sect, fdrive_t),
VMSTATE_UINT8(head, a_fdrive),
VMSTATE_UINT8(track, a_fdrive),
VMSTATE_UINT8(sect, a_fdrive),
VMSTATE_END_OF_LIST()
}
};
static void fdc_pre_save(const void *opaque)
{
fdctrl_t *s = (void *)opaque;
a_fdctrl *s = (void *)opaque;
s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
static int fdc_post_load(void *opaque)
{
fdctrl_t *s = opaque;
a_fdctrl *s = opaque;
SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
@ -668,46 +668,46 @@ static const VMStateDescription vmstate_fdc = {
.post_load = fdc_post_load,
.fields = (VMStateField []) {
/* Controller State */
VMSTATE_UINT8(sra, fdctrl_t),
VMSTATE_UINT8(srb, fdctrl_t),
VMSTATE_UINT8(dor_vmstate, fdctrl_t),
VMSTATE_UINT8(tdr, fdctrl_t),
VMSTATE_UINT8(dsr, fdctrl_t),
VMSTATE_UINT8(msr, fdctrl_t),
VMSTATE_UINT8(status0, fdctrl_t),
VMSTATE_UINT8(status1, fdctrl_t),
VMSTATE_UINT8(status2, fdctrl_t),
VMSTATE_UINT8(sra, a_fdctrl),
VMSTATE_UINT8(srb, a_fdctrl),
VMSTATE_UINT8(dor_vmstate, a_fdctrl),
VMSTATE_UINT8(tdr, a_fdctrl),
VMSTATE_UINT8(dsr, a_fdctrl),
VMSTATE_UINT8(msr, a_fdctrl),
VMSTATE_UINT8(status0, a_fdctrl),
VMSTATE_UINT8(status1, a_fdctrl),
VMSTATE_UINT8(status2, a_fdctrl),
/* Command FIFO */
VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
VMSTATE_UINT32(data_pos, fdctrl_t),
VMSTATE_UINT32(data_len, fdctrl_t),
VMSTATE_UINT8(data_state, fdctrl_t),
VMSTATE_UINT8(data_dir, fdctrl_t),
VMSTATE_UINT8(eot, fdctrl_t),
VMSTATE_VARRAY(fifo, a_fdctrl, fifo_size, 0, vmstate_info_uint8, uint8),
VMSTATE_UINT32(data_pos, a_fdctrl),
VMSTATE_UINT32(data_len, a_fdctrl),
VMSTATE_UINT8(data_state, a_fdctrl),
VMSTATE_UINT8(data_dir, a_fdctrl),
VMSTATE_UINT8(eot, a_fdctrl),
/* States kept only to be returned back */
VMSTATE_UINT8(timer0, fdctrl_t),
VMSTATE_UINT8(timer1, fdctrl_t),
VMSTATE_UINT8(precomp_trk, fdctrl_t),
VMSTATE_UINT8(config, fdctrl_t),
VMSTATE_UINT8(lock, fdctrl_t),
VMSTATE_UINT8(pwrd, fdctrl_t),
VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
vmstate_fdrive, fdrive_t),
VMSTATE_UINT8(timer0, a_fdctrl),
VMSTATE_UINT8(timer1, a_fdctrl),
VMSTATE_UINT8(precomp_trk, a_fdctrl),
VMSTATE_UINT8(config, a_fdctrl),
VMSTATE_UINT8(lock, a_fdctrl),
VMSTATE_UINT8(pwrd, a_fdctrl),
VMSTATE_UINT8_EQUAL(num_floppies, a_fdctrl),
VMSTATE_STRUCT_ARRAY(drives, a_fdctrl, MAX_FD, 1,
vmstate_fdrive, a_fdrive),
VMSTATE_END_OF_LIST()
}
};
static void fdctrl_external_reset(void *opaque)
{
fdctrl_t *s = opaque;
a_fdctrl *s = opaque;
fdctrl_reset(s, 0);
}
static void fdctrl_handle_tc(void *opaque, int irq, int level)
{
//fdctrl_t *s = opaque;
//a_fdctrl *s = opaque;
if (level) {
// XXX
@ -716,13 +716,13 @@ static void fdctrl_handle_tc(void *opaque, int irq, int level)
}
/* XXX: may change if moved to bdrv */
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num)
{
return fdctrl->drives[drive_num].drive;
}
/* Change IRQ state */
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
static void fdctrl_reset_irq (a_fdctrl *fdctrl)
{
if (!(fdctrl->sra & FD_SRA_INTPEND))
return;
@ -731,7 +731,7 @@ static void fdctrl_reset_irq (fdctrl_t *fdctrl)
fdctrl->sra &= ~FD_SRA_INTPEND;
}
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0)
{
/* Sparc mutation */
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
@ -751,7 +751,7 @@ static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
}
/* Reset controller */
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq)
{
int i;
@ -780,12 +780,12 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
}
}
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
static inline a_fdrive *drv0 (a_fdctrl *fdctrl)
{
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
}
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
static inline a_fdrive *drv1 (a_fdctrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
return &fdctrl->drives[1];
@ -794,7 +794,7 @@ static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
}
#if MAX_FD == 4
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
static inline a_fdrive *drv2 (a_fdctrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
return &fdctrl->drives[2];
@ -802,7 +802,7 @@ static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
return &fdctrl->drives[1];
}
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
static inline a_fdrive *drv3 (a_fdctrl *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
return &fdctrl->drives[3];
@ -811,7 +811,7 @@ static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
}
#endif
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
static a_fdrive *get_cur_drv (a_fdctrl *fdctrl)
{
switch (fdctrl->cur_drv) {
case 0: return drv0(fdctrl);
@ -825,7 +825,7 @@ static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
}
/* Status A register : 0x00 (read-only) */
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl)
{
uint32_t retval = fdctrl->sra;
@ -835,7 +835,7 @@ static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
}
/* Status B register : 0x01 (read-only) */
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl)
{
uint32_t retval = fdctrl->srb;
@ -845,7 +845,7 @@ static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
}
/* Digital output register : 0x02 */
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl)
{
uint32_t retval = fdctrl->dor;
@ -856,7 +856,7 @@ static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
return retval;
}
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value)
{
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
@ -895,7 +895,7 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
}
/* Tape drive register : 0x03 */
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl)
{
uint32_t retval = fdctrl->tdr;
@ -904,7 +904,7 @@ static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
return retval;
}
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@ -918,7 +918,7 @@ static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
}
/* Main status register : 0x04 (read) */
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl)
{
uint32_t retval = fdctrl->msr;
@ -931,7 +931,7 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
}
/* Data select rate register : 0x04 (write) */
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@ -951,7 +951,7 @@ static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
fdctrl->dsr = value;
}
static int fdctrl_media_changed(fdrive_t *drv)
static int fdctrl_media_changed(a_fdrive *drv)
{
int ret;
@ -965,7 +965,7 @@ static int fdctrl_media_changed(fdrive_t *drv)
}
/* Digital input register : 0x07 (read-only) */
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl)
{
uint32_t retval = 0;
@ -984,7 +984,7 @@ static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
}
/* FIFO state control */
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
static void fdctrl_reset_fifo (a_fdctrl *fdctrl)
{
fdctrl->data_dir = FD_DIR_WRITE;
fdctrl->data_pos = 0;
@ -992,7 +992,7 @@ static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
}
/* Set FIFO status for the host to read */
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq)
{
fdctrl->data_dir = FD_DIR_READ;
fdctrl->data_len = fifo_len;
@ -1003,7 +1003,7 @@ static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
}
/* Set an error: unimplemented/unknown command */
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction)
{
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
fdctrl->fifo[0] = FD_SR0_INVCMD;
@ -1011,7 +1011,7 @@ static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
}
/* Seek to next sector */
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv)
{
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
@ -1045,10 +1045,10 @@ static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
}
/* Callback for transfer end (stop or abort) */
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0,
uint8_t status1, uint8_t status2)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
@ -1071,9 +1071,9 @@ static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
}
/* Prepare a data transfer (either DMA or FIFO) */
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
uint8_t kh, kt, ks;
int did_seek = 0;
@ -1173,7 +1173,7 @@ static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
}
/* Prepare a transfer of deleted data */
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction)
{
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
@ -1187,8 +1187,8 @@ static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len)
{
fdctrl_t *fdctrl;
fdrive_t *cur_drv;
a_fdctrl *fdctrl;
a_fdrive *cur_drv;
int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
@ -1294,9 +1294,9 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
}
/* Data register : 0x05 */
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
static uint32_t fdctrl_read_data (a_fdctrl *fdctrl)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
uint32_t retval = 0;
int pos;
@ -1342,9 +1342,9 @@ static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
return retval;
}
static void fdctrl_format_sector (fdctrl_t *fdctrl)
static void fdctrl_format_sector (a_fdctrl *fdctrl)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
uint8_t kh, kt, ks;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
@ -1404,16 +1404,16 @@ static void fdctrl_format_sector (fdctrl_t *fdctrl)
}
}
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_lock (a_fdctrl *fdctrl, int direction)
{
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
fdctrl->fifo[0] = fdctrl->lock << 4;
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
}
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
fdctrl->fifo[0] = drv0(fdctrl)->track;
@ -1436,22 +1436,22 @@ static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 10, 0);
}
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_version (a_fdctrl *fdctrl, int direction)
{
/* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
}
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_partid (a_fdctrl *fdctrl, int direction)
{
fdctrl->fifo[0] = 0x41; /* Stepping 1 */
fdctrl_set_fifo(fdctrl, 1, 0);
}
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
drv0(fdctrl)->track = fdctrl->fifo[3];
@ -1472,9 +1472,9 @@ static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
fdctrl->fifo[0] = 0;
fdctrl->fifo[1] = 0;
@ -1502,9 +1502,9 @@ static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 15, 1);
}
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
@ -1512,9 +1512,9 @@ static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1541,7 +1541,7 @@ static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction)
{
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
fdctrl->timer1 = fdctrl->fifo[2] >> 1;
@ -1553,9 +1553,9 @@ static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1569,9 +1569,9 @@ static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 1, 0);
}
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1581,9 +1581,9 @@ static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
if(fdctrl->reset_sensei > 0) {
fdctrl->fifo[0] =
@ -1603,9 +1603,9 @@ static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int directio
fdctrl->status0 = FD_SR0_RDYCHG;
}
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1619,9 +1619,9 @@ static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
}
}
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[1] & 0x80)
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
@ -1629,7 +1629,7 @@ static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction)
{
fdctrl->config = fdctrl->fifo[2];
fdctrl->precomp_trk = fdctrl->fifo[3];
@ -1637,22 +1637,22 @@ static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_powerdown_mode (a_fdctrl *fdctrl, int direction)
{
fdctrl->pwrd = fdctrl->fifo[1];
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl_set_fifo(fdctrl, 1, 1);
}
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_option (a_fdctrl *fdctrl, int direction)
{
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
/* Command parameters done */
@ -1672,9 +1672,9 @@ static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int dir
}
}
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1688,9 +1688,9 @@ static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
static void fdctrl_handle_relative_seek_in (a_fdctrl *fdctrl, int direction)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@ -1709,7 +1709,7 @@ static const struct {
uint8_t mask;
const char* name;
int parameters;
void (*handler)(fdctrl_t *fdctrl, int direction);
void (*handler)(a_fdctrl *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
@ -1748,9 +1748,9 @@ static const struct {
/* Associate command to an index in the 'handlers' array */
static uint8_t command_to_handler[256];
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value)
{
fdrive_t *cur_drv;
a_fdrive *cur_drv;
int pos;
/* Reset mode */
@ -1815,8 +1815,8 @@ static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
static void fdctrl_result_timer(void *opaque)
{
fdctrl_t *fdctrl = opaque;
fdrive_t *cur_drv = get_cur_drv(fdctrl);
a_fdctrl *fdctrl = opaque;
a_fdrive *cur_drv = get_cur_drv(fdctrl);
/* Pretend we are spinning.
* This is needed for Coherent, which uses READ ID to check for
@ -1829,7 +1829,7 @@ static void fdctrl_result_timer(void *opaque)
}
/* Init functions */
static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds)
{
unsigned int i;
@ -1839,14 +1839,14 @@ static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
}
}
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
a_fdctrl *fdctrl_init_isa(BlockDriverState **fds)
{
fdctrl_t *fdctrl;
a_fdctrl *fdctrl;
ISADevice *dev;
int dma_chann = 2;
dev = isa_create_simple("isa-fdc");
fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
fdctrl = &(DO_UPCAST(a_fdctrl_isabus, busdev, dev)->state);
fdctrl->dma_chann = dma_chann;
DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
@ -1856,17 +1856,17 @@ fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
return fdctrl;
}
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base,
a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a_target_phys_addr mmio_base,
BlockDriverState **fds)
{
fdctrl_t *fdctrl;
a_fdctrl *fdctrl;
DeviceState *dev;
fdctrl_sysbus_t *sys;
a_fdctrl_sysbus *sys;
dev = qdev_create(NULL, "sysbus-fdc");
qdev_init(dev);
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
@ -1878,16 +1878,16 @@ fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
return fdctrl;
}
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
BlockDriverState **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
fdctrl_sysbus_t *sys;
fdctrl_t *fdctrl;
a_fdctrl_sysbus *sys;
a_fdctrl *fdctrl;
dev = qdev_create(NULL, "SUNW,fdtwo");
qdev_init(dev);
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, io_base);
@ -1900,7 +1900,7 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
return fdctrl;
}
static int fdctrl_init_common(fdctrl_t *fdctrl)
static int fdctrl_init_common(a_fdctrl *fdctrl)
{
int i, j;
static int command_tables_inited = 0;
@ -1935,8 +1935,8 @@ static int fdctrl_init_common(fdctrl_t *fdctrl)
static int isabus_fdc_init1(ISADevice *dev)
{
fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
fdctrl_t *fdctrl = &isa->state;
a_fdctrl_isabus *isa = DO_UPCAST(a_fdctrl_isabus, busdev, dev);
a_fdctrl *fdctrl = &isa->state;
int iobase = 0x3f0;
int isairq = 6;
@ -1955,7 +1955,7 @@ static int isabus_fdc_init1(ISADevice *dev)
static int sysbus_fdc_init1(SysBusDevice *dev)
{
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
@ -1968,7 +1968,7 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
static int sun4m_fdc_init1(SysBusDevice *dev)
{
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
@ -1984,19 +1984,19 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
static ISADeviceInfo isa_fdc_info = {
.init = isabus_fdc_init1,
.qdev.name = "isa-fdc",
.qdev.size = sizeof(fdctrl_isabus_t),
.qdev.size = sizeof(a_fdctrl_isabus),
};
static SysBusDeviceInfo sysbus_fdc_info = {
.init = sysbus_fdc_init1,
.qdev.name = "sysbus-fdc",
.qdev.size = sizeof(fdctrl_sysbus_t),
.qdev.size = sizeof(a_fdctrl_sysbus),
};
static SysBusDeviceInfo sun4m_fdc_info = {
.init = sun4m_fdc_init1,
.qdev.name = "SUNW,fdtwo",
.qdev.size = sizeof(fdctrl_sysbus_t),
.qdev.size = sizeof(a_fdctrl_sysbus),
};
static void fdc_register_devices(void)

12
hw/fdc.h
View file

@ -1,12 +1,12 @@
/* fdc.c */
#define MAX_FD 2
typedef struct fdctrl_t fdctrl_t;
typedef struct fdctrl a_fdctrl;
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds);
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base,
a_fdctrl *fdctrl_init_isa(BlockDriverState **fds);
a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a_target_phys_addr mmio_base,
BlockDriverState **fds);
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
BlockDriverState **fds, qemu_irq *fdc_tc);
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num);

8
hw/flash.h
View file

@ -1,15 +1,15 @@
/* NOR flash devices */
typedef struct pflash_t pflash_t;
typedef struct pflash a_pflash;
/* pflash_cfi01.c */
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
@ -36,7 +36,7 @@ uint8_t nand_getio(NANDFlashState *s);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_update(void *opaque, a_target_phys_addr new);
void onenand_base_unmap(void *opaque);
void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);

12
hw/framebuffer.c
View file

@ -22,7 +22,7 @@
void framebuffer_update_display(
DisplayState *ds,
target_phys_addr_t base,
a_target_phys_addr base,
int cols, /* Width in pixels. */
int rows, /* Leight in pixels. */
int src_width, /* Length of source line, in bytes. */
@ -34,16 +34,16 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
target_phys_addr_t src_len;
a_target_phys_addr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
ram_addr_t addr;
ram_addr_t pd;
ram_addr_t pd2;
a_ram_addr addr;
a_ram_addr pd;
a_ram_addr pd2;
i = *first_row;
*first_row = -1;
@ -86,7 +86,7 @@ void framebuffer_update_display(
dest += i * dest_row_pitch;
for (; i < rows; i++) {
target_phys_addr_t dirty_offset;
a_target_phys_addr dirty_offset;
dirty = 0;
dirty_offset = 0;
while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) {

2
hw/framebuffer.h
View file

@ -7,7 +7,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
target_phys_addr_t base,
a_target_phys_addr base,
int cols,
int rows,
int src_width,

8
hw/fw_cfg.c
View file

@ -116,18 +116,18 @@ static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
fw_cfg_select(opaque, (uint16_t)value);
}
static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
static uint32_t fw_cfg_mem_readb(void *opaque, a_target_phys_addr addr)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
static void fw_cfg_mem_writeb(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
fw_cfg_write(opaque, (uint8_t)value);
}
static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
static void fw_cfg_mem_writew(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
fw_cfg_select(opaque, (uint16_t)value);
@ -242,7 +242,7 @@ int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
}
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
a_target_phys_addr ctl_addr, a_target_phys_addr data_addr)
{
FWCfgState *s;
int io_ctl_memory, io_data_memory;

2
hw/fw_cfg.h
View file

@ -35,7 +35,7 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value);
int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
a_target_phys_addr crl_addr, a_target_phys_addr data_addr);
#endif /* NO_QEMU_PROTOS */

34
hw/g364fb.c
View file

@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State {
/* hardware */
uint8_t *vram;
ram_addr_t vram_offset;
a_ram_addr vram_offset;
int vram_size;
qemu_irq irq;
/* registers */
@ -68,13 +68,13 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
static inline int check_dirty(ram_addr_t page)
static inline int check_dirty(a_ram_addr page)
{
return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
}
static inline void reset_dirty(G364State *s,
ram_addr_t page_min, ram_addr_t page_max)
a_ram_addr page_min, a_ram_addr page_max)
{
cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
VGA_DIRTY_FLAG);
@ -85,7 +85,7 @@ static void g364fb_draw_graphic8(G364State *s)
int i, w;
uint8_t *vram;
uint8_t *data_display, *dd;
ram_addr_t page, page_min, page_max;
a_ram_addr page, page_min, page_max;
int x, y;
int xmin, xmax;
int ymin, ymax;
@ -115,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
page = s->vram_offset;
page_min = (ram_addr_t)-1;
page_min = (a_ram_addr)-1;
page_max = 0;
x = y = 0;
@ -138,7 +138,7 @@ static void g364fb_draw_graphic8(G364State *s)
if (check_dirty(page)) {
if (y < ymin)
ymin = ymax = y;
if (page_min == (ram_addr_t)-1)
if (page_min == (a_ram_addr)-1)
page_min = page;
page_max = page;
if (x < xmin)
@ -197,9 +197,9 @@ static void g364fb_draw_graphic8(G364State *s)
ymax = y;
} else {
int dy;
if (page_min != (ram_addr_t)-1) {
if (page_min != (a_ram_addr)-1) {
reset_dirty(s, page_min, page_max);
page_min = (ram_addr_t)-1;
page_min = (a_ram_addr)-1;
page_max = 0;
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
xmin = s->width;
@ -219,7 +219,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
done:
if (page_min != (ram_addr_t)-1) {
if (page_min != (a_ram_addr)-1) {
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
reset_dirty(s, page_min, page_max);
}
@ -336,7 +336,7 @@ static void g364fb_screen_dump(void *opaque, const char *filename)
}
/* called for accesses to io ports */
static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
{
G364State *s = opaque;
uint32_t val;
@ -379,7 +379,7 @@ static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
if (addr & 0x2)
@ -388,7 +388,7 @@ static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
return v & 0xffff;
}
static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
static uint32_t g364fb_ctrl_readb(void *opaque, a_target_phys_addr addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
@ -415,7 +415,7 @@ static void g364_invalidate_cursor_position(G364State *s)
}
}
static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
G364State *s = opaque;
@ -490,7 +490,7 @@ static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t v
qemu_irq_lower(s->irq);
}
static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@ -501,7 +501,7 @@ static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void g364fb_ctrl_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@ -583,8 +583,8 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
int g364fb_mm_init(a_target_phys_addr vram_base,
a_target_phys_addr ctrl_base, int it_shift,
qemu_irq irq)
{
G364State *s;

6
hw/grackle_pci.c
View file

@ -37,7 +37,7 @@
#define GRACKLE_DPRINTF(fmt, ...)
#endif
typedef target_phys_addr_t pci_addr_t;
typedef a_target_phys_addr a_pci_addr;
#include "pci_host.h"
typedef struct GrackleState {
@ -45,7 +45,7 @@ typedef struct GrackleState {
PCIHostState host_state;
} GrackleState;
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
GrackleState *s = opaque;
@ -58,7 +58,7 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
s->host_state.config_reg = val;
}
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr)
{
GrackleState *s = opaque;
uint32_t val;

22
hw/gt64xxx.c
View file

@ -27,7 +27,7 @@
#include "pci.h"
#include "pc.h"
typedef target_phys_addr_t pci_addr_t;
typedef a_target_phys_addr a_pci_addr;
#include "pci_host.h"
//#define DEBUG
@ -229,8 +229,8 @@ typedef target_phys_addr_t pci_addr_t;
typedef PCIHostState GT64120PCIState;
#define PCI_MAPPING_ENTRY(regname) \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
a_target_phys_addr regname ##_start; \
a_target_phys_addr regname ##_length; \
int regname ##_handle
typedef struct GT64120State {
@ -243,11 +243,11 @@ typedef struct GT64120State {
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
static void check_reserved_space (target_phys_addr_t *start,
target_phys_addr_t *length)
static void check_reserved_space (a_target_phys_addr *start,
a_target_phys_addr *length)
{
target_phys_addr_t begin = *start;
target_phys_addr_t end = *start + *length;
a_target_phys_addr begin = *start;
a_target_phys_addr end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@ -269,8 +269,8 @@ static void check_reserved_space (target_phys_addr_t *start,
static void gt64120_isd_mapping(GT64120State *s)
{
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
a_target_phys_addr start = s->regs[GT_ISD] << 21;
a_target_phys_addr length = 0x1000;
if (s->ISD_length)
cpu_register_physical_memory(s->ISD_start, s->ISD_length,
@ -303,7 +303,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
}
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
static void gt64120_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
GT64120State *s = opaque;
@ -583,7 +583,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
}
static uint32_t gt64120_readl (void *opaque,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
GT64120State *s = opaque;
uint32_t val;

4
hw/gumstix.c
View file

@ -41,7 +41,7 @@
static const int sector_len = 128 * 1024;
static void connex_init(ram_addr_t ram_size,
static void connex_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -75,7 +75,7 @@ static void connex_init(ram_addr_t ram_size,
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
static void verdex_init(ram_addr_t ram_size,
static void verdex_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/heathrow_pic.c
View file

@ -62,7 +62,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
}
}
static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;
@ -92,7 +92,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;

12
hw/hpet.c
View file

@ -270,20 +270,20 @@ static void hpet_del_timer(HPETTimer *t)
}
#ifdef HPET_DEBUG
static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readb(void *opaque, a_target_phys_addr addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readw(void *opaque, a_target_phys_addr addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr)
{
HPETState *s = (HPETState *)opaque;
uint64_t cur_tick, index;
@ -350,14 +350,14 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
}
#ifdef HPET_DEBUG
static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
static void hpet_ram_writeb(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
addr, value);
}
static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
static void hpet_ram_writew(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
@ -365,7 +365,7 @@ static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
}
#endif
static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
static void hpet_ram_writel(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
int i;

2
hw/ide.h
View file

@ -18,7 +18,7 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);

12
hw/ide/macio.c
View file

@ -178,7 +178,7 @@ static void pmac_ide_flush(DBDMA_io *io)
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
target_phys_addr_t addr, uint32_t val)
a_target_phys_addr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -196,7 +196,7 @@ static void pmac_ide_writeb (void *opaque,
}
}
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@ -218,7 +218,7 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
}
static void pmac_ide_writew (void *opaque,
target_phys_addr_t addr, uint32_t val)
a_target_phys_addr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -231,7 +231,7 @@ static void pmac_ide_writew (void *opaque,
}
}
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@ -249,7 +249,7 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
}
static void pmac_ide_writel (void *opaque,
target_phys_addr_t addr, uint32_t val)
a_target_phys_addr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@ -262,7 +262,7 @@ static void pmac_ide_writel (void *opaque,
}
}
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
static uint32_t pmac_ide_readl (void *opaque,a_target_phys_addr addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;

10
hw/ide/mmio.c
View file

@ -41,7 +41,7 @@ typedef struct {
int shift;
} MMIOState;
static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr)
{
MMIOState *s = (MMIOState*)opaque;
IDEBus *bus = s->bus;
@ -52,7 +52,7 @@ static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
return ide_data_readw(bus, 0);
}
static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
static void mmio_ide_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@ -76,14 +76,14 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
mmio_ide_write,
};
static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
static uint32_t mmio_ide_status_read (void *opaque, a_target_phys_addr addr)
{
MMIOState *s= (MMIOState*)opaque;
IDEBus *bus = s->bus;
return ide_status_read(bus, 0);
}
static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
static void mmio_ide_cmd_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@ -122,7 +122,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
return 0;
}
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
{

16
hw/integratorcp.c
View file

@ -37,7 +37,7 @@ static uint8_t integrator_spd[128] = {
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static uint32_t integratorcm_read(void *opaque, a_target_phys_addr offset)
{
integratorcm_state *s = (integratorcm_state *)opaque;
if (offset >= 0x100 && offset < 0x200) {
@ -138,7 +138,7 @@ static void integratorcm_update(integratorcm_state *s)
hw_error("Core module interrupt\n");
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
static void integratorcm_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@ -296,7 +296,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int level)
icp_pic_update(s);
}
static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -324,7 +324,7 @@ static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
}
}
static void icp_pic_write(void *opaque, target_phys_addr_t offset,
static void icp_pic_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@ -388,7 +388,7 @@ static int icp_pic_init(SysBusDevice *dev)
}
/* CP control registers. */
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
{
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
@ -405,7 +405,7 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
}
}
static void icp_control_write(void *opaque, target_phys_addr_t offset,
static void icp_control_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
switch (offset >> 2) {
@ -448,13 +448,13 @@ static struct arm_boot_info integrator_binfo = {
.board_id = 0x113,
};
static void integratorcp_init(ram_addr_t ram_size,
static void integratorcp_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset;
a_ram_addr ram_offset;
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;

4
hw/ioapic.c
View file

@ -119,7 +119,7 @@ void ioapic_set_irq(void *opaque, int vector, int level)
}
}
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
{
IOAPICState *s = opaque;
int index;
@ -155,7 +155,7 @@ static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
IOAPICState *s = opaque;
int index;

26
hw/iommu.c
View file

@ -130,15 +130,15 @@
typedef struct IOMMUState {
SysBusDevice busdev;
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
a_target_phys_addr iostart;
uint32_t version;
qemu_irq irq;
} IOMMUState;
static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
a_target_phys_addr saddr;
uint32_t ret;
saddr = addr >> 2;
@ -156,11 +156,11 @@ static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
static void iommu_mem_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
a_target_phys_addr saddr;
saddr = addr >> 2;
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
@ -250,12 +250,12 @@ static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
iommu_mem_writel,
};
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr)
{
uint32_t ret;
target_phys_addr_t iopte;
a_target_phys_addr iopte;
#ifdef DEBUG_IOMMU
target_phys_addr_t pa = addr;
a_target_phys_addr pa = addr;
#endif
iopte = s->regs[IOMMU_BASE] << 4;
@ -269,11 +269,11 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
return ret;
}
static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr,
uint32_t pte)
{
uint32_t tmppte;
target_phys_addr_t pa;
a_target_phys_addr pa;
tmppte = pte;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
@ -283,7 +283,7 @@ static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
return pa;
}
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr,
int is_write)
{
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
@ -295,12 +295,12 @@ static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
qemu_irq_raise(s->irq);
}
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
void sparc_iommu_memory_rw(void *opaque, a_target_phys_addr addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
target_phys_addr_t page, phys_addr;
a_target_phys_addr page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;

4
hw/isa.h
View file

@ -30,9 +30,9 @@ void isa_qdev_register(ISADeviceInfo *info);
ISADevice *isa_create(const char *name);
ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
extern a_target_phys_addr isa_mem_base;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size);
/* dma.c */
int DMA_get_channel_mode (int nchan);

14
hw/isa_mmio.c
View file

@ -25,13 +25,13 @@
#include "hw.h"
#include "isa.h"
static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
static void isa_mmio_writeb (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
static void isa_mmio_writew (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -40,7 +40,7 @@ static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
cpu_outw(addr & IOPORTS_MASK, val);
}
static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
static void isa_mmio_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@ -49,7 +49,7 @@ static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -57,7 +57,7 @@ static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -68,7 +68,7 @@ static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
static uint32_t isa_mmio_readl (void *opaque, a_target_phys_addr addr)
{
uint32_t val;
@ -93,7 +93,7 @@ static CPUReadMemoryFunc * const isa_mmio_read[] = {
static int isa_mmio_iomemtype = 0;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size)
{
if (!isa_mmio_iomemtype) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,

20
hw/jazz_led.c
View file

@ -31,15 +31,15 @@
typedef enum {
REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2,
} screen_state_t;
} e_screen_state;
typedef struct LedState {
uint8_t segments;
DisplayState *ds;
screen_state_t state;
e_screen_state state;
} LedState;
static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
static uint32_t led_readb(void *opaque, a_target_phys_addr addr)
{
LedState *s = opaque;
uint32_t val;
@ -58,7 +58,7 @@ static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
static uint32_t led_readw(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -71,7 +71,7 @@ static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
return v;
}
static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
static uint32_t led_readl(void *opaque, a_target_phys_addr addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@ -88,7 +88,7 @@ static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
return v;
}
static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LedState *s = opaque;
@ -105,7 +105,7 @@ static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 8) & 0xff);
@ -116,7 +116,7 @@ static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
#endif
}
static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void led_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 24) & 0xff);
@ -282,7 +282,7 @@ static void jazz_led_screen_dump(void *opaque, const char *filename)
printf("jazz_led_screen_dump() not implemented\n");
}
static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
static void jazz_led_text_update(void *opaque, a_console_ch *chardata)
{
LedState *s = opaque;
char buf[2];
@ -298,7 +298,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
void jazz_led_init(target_phys_addr_t base)
void jazz_led_init(a_target_phys_addr base)
{
LedState *s;
int io;

30
hw/loader.c
View file

@ -81,10 +81,10 @@ int load_image(const char *filename, uint8_t *addr)
}
/* return the amount read, just like fread. 0 may mean error or eof */
int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
{
uint8_t buf[4096];
target_phys_addr_t dst_begin = dst_addr;
a_target_phys_addr dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@ -101,16 +101,16 @@ int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
}
/* returns 0 on error, 1 if ok */
int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
{
return fread_targphys(dst_addr, nbytes, f) == nbytes;
}
/* read()-like version */
int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes)
int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes)
{
uint8_t buf[4096];
target_phys_addr_t dst_begin = dst_addr;
a_target_phys_addr dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@ -127,7 +127,7 @@ int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes)
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
target_phys_addr_t addr, int max_sz)
a_target_phys_addr addr, int max_sz)
{
FILE *f;
size_t got;
@ -142,7 +142,7 @@ int load_image_targphys(const char *filename,
return got;
}
void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
const char *source)
{
static const uint8_t nul_byte = 0;
@ -204,8 +204,8 @@ static void bswap_ahdr(struct exec *e)
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
int bswap_needed, target_phys_addr_t target_page_size)
int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
int bswap_needed, a_target_phys_addr target_page_size)
{
int fd, size, ret;
struct exec e;
@ -358,7 +358,7 @@ int load_elf(const char *filename, int64_t address_offset,
return -1;
}
static void bswap_uboot_header(uboot_image_header_t *hdr)
static void bswap_uboot_header(an_uboot_image_header *hdr)
{
#ifndef HOST_WORDS_BIGENDIAN
bswap32s(&hdr->ih_magic);
@ -457,13 +457,13 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src,
}
/* Load a U-Boot image. */
int load_uimage(const char *filename, target_phys_addr_t *ep,
target_phys_addr_t *loadaddr, int *is_linux)
int load_uimage(const char *filename, a_target_phys_addr *ep,
a_target_phys_addr *loadaddr, int *is_linux)
{
int fd;
int size;
uboot_image_header_t h;
uboot_image_header_t *hdr = &h;
an_uboot_image_header h;
an_uboot_image_header *hdr = &h;
uint8_t *data = NULL;
int ret = -1;
@ -471,7 +471,7 @@ int load_uimage(const char *filename, target_phys_addr_t *ep,
if (fd < 0)
return -1;
size = read(fd, hdr, sizeof(uboot_image_header_t));
size = read(fd, hdr, sizeof(an_uboot_image_header));
if (size < 0)
goto out;

18
hw/loader.h
View file

@ -4,18 +4,18 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz);
int load_image_targphys(const char *filename, a_target_phys_addr, int max_sz);
int load_elf(const char *filename, int64_t address_offset,
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr,
int big_endian, int elf_machine, int clear_lsb);
int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
int bswap_needed, target_phys_addr_t target_page_size);
int load_uimage(const char *filename, target_phys_addr_t *ep,
target_phys_addr_t *loadaddr, int *is_linux);
int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
int bswap_needed, a_target_phys_addr target_page_size);
int load_uimage(const char *filename, a_target_phys_addr *ep,
a_target_phys_addr *loadaddr, int *is_linux);
int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes);
void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes);
void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
const char *source);
#endif

26
hw/lsi53c895a.c
View file

@ -484,7 +484,7 @@ static void lsi_resume_script(LSIState *s)
static void lsi_do_dma(LSIState *s, int out)
{
uint32_t count;
target_phys_addr_t addr;
a_target_phys_addr addr;
if (!s->current_dma_len) {
/* Wait until data is available. */
@ -1723,14 +1723,14 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
#undef CASE_SET_REG32
}
static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
lsi_reg_writeb(s, addr & 0xff, val);
}
static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
@ -1739,7 +1739,7 @@ static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
}
static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
@ -1750,14 +1750,14 @@ static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_mmio_readb(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1768,7 +1768,7 @@ static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_mmio_readl(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1792,7 +1792,7 @@ static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
lsi_mmio_writel,
};
static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@ -1806,7 +1806,7 @@ static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->script_ram[addr >> 2] = newval;
}
static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@ -1822,7 +1822,7 @@ static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
}
static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
LSIState *s = opaque;
@ -1830,7 +1830,7 @@ static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
s->script_ram[addr >> 2] = val;
}
static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1841,7 +1841,7 @@ static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
return val & 0xff;
}
static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;
uint32_t val;
@ -1853,7 +1853,7 @@ static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
return le16_to_cpu(val);
}
static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
static uint32_t lsi_ram_readl(void *opaque, a_target_phys_addr addr)
{
LSIState *s = opaque;

72
hw/m48t59.c
View file

@ -41,7 +41,7 @@
* alarm and a watchdog timer and related control registers. In the
* PPC platform there is also a nvram lock function.
*/
struct m48t59_t {
struct m48t59 {
/* Model parameters */
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
@ -63,12 +63,12 @@ struct m48t59_t {
typedef struct M48t59ISAState {
ISADevice busdev;
m48t59_t state;
a_m48t59 state;
} M48t59ISAState;
typedef struct M48t59SysBusState {
SysBusDevice busdev;
m48t59_t state;
a_m48t59 state;
} M48t59SysBusState;
/* Fake timer functions */
@ -88,7 +88,7 @@ static void alarm_cb (void *opaque)
{
struct tm tm;
uint64_t next_time;
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
@ -130,7 +130,7 @@ static void alarm_cb (void *opaque)
qemu_set_irq(NVRAM->IRQ, 0);
}
static void set_alarm (m48t59_t *NVRAM)
static void set_alarm (a_m48t59 *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
@ -142,12 +142,12 @@ static void set_alarm (m48t59_t *NVRAM)
}
/* RTC management helpers */
static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
static inline void get_time (a_m48t59 *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
static void set_time (m48t59_t *NVRAM, struct tm *tm)
static void set_time (a_m48t59 *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
@ -156,7 +156,7 @@ static void set_time (m48t59_t *NVRAM, struct tm *tm)
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
@ -170,7 +170,7 @@ static void watchdog_cb (void *opaque)
}
}
static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
@ -188,7 +188,7 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
struct tm tm;
int tmp;
@ -356,7 +356,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
@ -463,14 +463,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
void m48t59_set_addr (void *opaque, uint32_t addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
@ -478,7 +478,7 @@ void m48t59_toggle_lock (void *opaque, int lock)
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
@ -502,7 +502,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
@ -519,24 +519,24 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
return retval;
}
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@ -544,18 +544,18 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
return retval;
}
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
@ -563,9 +563,9 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
return retval;
}
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
@ -589,7 +589,7 @@ static CPUReadMemoryFunc * const nvram_read[] = {
static void m48t59_save(QEMUFile *f, void *opaque)
{
m48t59_t *s = opaque;
a_m48t59 *s = opaque;
qemu_put_8s(f, &s->lock);
qemu_put_be16s(f, &s->addr);
@ -598,7 +598,7 @@ static void m48t59_save(QEMUFile *f, void *opaque)
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
m48t59_t *s = opaque;
a_m48t59 *s = opaque;
if (version_id != 1)
return -EINVAL;
@ -612,7 +612,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
static void m48t59_reset(void *opaque)
{
m48t59_t *NVRAM = opaque;
a_m48t59 *NVRAM = opaque;
NVRAM->addr = 0;
NVRAM->lock = 0;
@ -624,7 +624,7 @@ static void m48t59_reset(void *opaque)
}
/* Initialisation routine */
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
uint32_t io_base, uint16_t size,
int type)
{
@ -652,11 +652,11 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
return &d->state;
}
m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
M48t59ISAState *d;
ISADevice *dev;
m48t59_t *s;
a_m48t59 *s;
dev = isa_create("m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type);
@ -674,7 +674,7 @@ m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
return s;
}
static void m48t59_init_common(m48t59_t *s)
static void m48t59_init_common(a_m48t59 *s)
{
s->buffer = qemu_mallocz(s->size);
if (s->type == 59) {
@ -690,7 +690,7 @@ static void m48t59_init_common(m48t59_t *s)
static int m48t59_init_isa1(ISADevice *dev)
{
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
m48t59_t *s = &d->state;
a_m48t59 *s = &d->state;
isa_init_irq(dev, &s->IRQ, 8);
m48t59_init_common(s);
@ -701,7 +701,7 @@ static int m48t59_init_isa1(ISADevice *dev)
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
m48t59_t *s = &d->state;
a_m48t59 *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);

4
hw/mac_dbdma.c
View file

@ -693,7 +693,7 @@ dbdma_control_write(DBDMA_channel *ch)
}
static void dbdma_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
a_target_phys_addr addr, uint32_t value)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
@ -741,7 +741,7 @@ static void dbdma_writel (void *opaque,
}
}
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
static uint32_t dbdma_readl (void *opaque, a_target_phys_addr addr)
{
uint32_t value;
int channel = addr >> DBDMA_CHANNEL_SHIFT;

2
hw/mac_dbdma.h
View file

@ -28,7 +28,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
void *opaque;
void *channel;
target_phys_addr_t addr;
a_target_phys_addr addr;
int len;
int is_last;
int is_dma_out;

10
hw/mac_nvram.c
View file

@ -38,7 +38,7 @@
#endif
struct MacIONVRAMState {
target_phys_addr_t size;
a_target_phys_addr size;
int mem_index;
unsigned int it_shift;
uint8_t *data;
@ -72,7 +72,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
/* macio style NVRAM device */
static void macio_nvram_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
a_target_phys_addr addr, uint32_t value)
{
MacIONVRAMState *s = opaque;
@ -81,7 +81,7 @@ static void macio_nvram_writeb (void *opaque,
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
static uint32_t macio_nvram_readb (void *opaque, a_target_phys_addr addr)
{
MacIONVRAMState *s = opaque;
uint32_t value;
@ -128,7 +128,7 @@ static void macio_nvram_reset(void *opaque)
{
}
MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
unsigned int it_shift)
{
MacIONVRAMState *s;
@ -148,7 +148,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
return s;
}
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
void macio_nvram_map (void *opaque, a_target_phys_addr mem_base)
{
MacIONVRAMState *s;

14
hw/macio.c
View file

@ -27,8 +27,8 @@
#include "pci.h"
#include "escc.h"
typedef struct macio_state_t macio_state_t;
struct macio_state_t {
typedef struct macio_state a_macio_state;
struct macio_state {
int is_oldworld;
int pic_mem_index;
int dbdma_mem_index;
@ -42,10 +42,10 @@ struct macio_state_t {
static void macio_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
macio_state_t *macio_state;
a_macio_state *macio_state;
int i;
macio_state = (macio_state_t *)(pci_dev + 1);
macio_state = (a_macio_state *)(pci_dev + 1);
if (macio_state->pic_mem_index >= 0) {
if (macio_state->is_oldworld) {
/* Heathrow PIC */
@ -84,13 +84,13 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int nb_ide, int *ide_mem_index, int escc_mem_index)
{
PCIDevice *d;
macio_state_t *macio_state;
a_macio_state *macio_state;
int i;
d = pci_register_device(bus, "macio",
sizeof(PCIDevice) + sizeof(macio_state_t),
sizeof(PCIDevice) + sizeof(a_macio_state),
-1, NULL, NULL);
macio_state = (macio_state_t *)(d + 1);
macio_state = (a_macio_state *)(d + 1);
macio_state->is_oldworld = is_oldworld;
macio_state->pic_mem_index = pic_mem_index;
macio_state->dbdma_mem_index = dbdma_mem_index;

6
hw/mainstone.c
View file

@ -68,13 +68,13 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(ram_addr_t ram_size,
static void mainstone_common_init(a_ram_addr ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
a_target_phys_addr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
qemu_irq *mst_irq;
DriveInfo *dinfo;
@ -127,7 +127,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
arm_load_kernel(cpu->env, &mainstone_binfo);
}
static void mainstone_init(ram_addr_t ram_size,
static void mainstone_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/marvell_88w8618_audio.c
View file

@ -133,7 +133,7 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
wm8750_set_bclk_in(s->wm, rate);
}
static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset)
{
mv88w8618_audio_state *s = opaque;
@ -158,7 +158,7 @@ static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
}
}
static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_audio_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mv88w8618_audio_state *s = opaque;

14
hw/mc146818rtc.c
View file

@ -659,7 +659,7 @@ static void mc146818rtc_register(void)
device_init(mc146818rtc_register)
/* Memory mapped interface */
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr)
{
RTCState *s = opaque;
@ -667,14 +667,14 @@ static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
}
static void cmos_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
a_target_phys_addr addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr)
{
RTCState *s = opaque;
uint32_t val;
@ -687,7 +687,7 @@ static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
}
static void cmos_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
a_target_phys_addr addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -696,7 +696,7 @@ static void cmos_mm_writew (void *opaque,
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr)
{
RTCState *s = opaque;
uint32_t val;
@ -709,7 +709,7 @@ static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
}
static void cmos_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
a_target_phys_addr addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -730,7 +730,7 @@ static CPUWriteMemoryFunc * const rtc_mm_write[] = {
&cmos_mm_writel,
};
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq,
int base_year)
{
RTCState *s;

10
hw/mcf.h
View file

@ -3,17 +3,17 @@
/* Motorola ColdFire device prototypes. */
/* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr);
void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env);
/* mcf_fec.c */
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);

20
hw/mcf5206.c
View file

@ -367,10 +367,10 @@ static const int m5206_mbar_width[] =
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset);
static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset);
static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
@ -388,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
return m5206_mbar_read(s, offset);
}
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@ -412,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
return m5206_mbar_read(s, offset);
}
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@ -430,12 +430,12 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
return m5206_mbar_read(s, offset);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
uint32_t value);
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
uint32_t value);
static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@ -459,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
m5206_mbar_write(s, offset, value);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@ -487,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
m5206_mbar_write(s, offset, value);
}
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;

12
hw/mcf5208.c
View file

@ -42,7 +42,7 @@ static void m5208_timer_update(m5208_timer_state *s)
qemu_irq_lower(s->irq);
}
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
static void m5208_timer_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@ -104,7 +104,7 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@ -132,7 +132,7 @@ static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write
};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
{
switch (addr) {
case 0x110: /* SDCS0 */
@ -153,7 +153,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
}
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
static void m5208_sys_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
@ -195,7 +195,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
}
static void mcf5208evb_init(ram_addr_t ram_size,
static void mcf5208evb_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -203,7 +203,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
a_target_phys_addr entry;
qemu_irq *pic;
if (!cpu_model)

6
hw/mcf_fec.c
View file

@ -214,7 +214,7 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
}
}
static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void mcf_fec_write(void *opaque, a_target_phys_addr addr, uint32_t value)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@ -450,7 +450,7 @@ static void mcf_fec_cleanup(VLANClientState *vc)
qemu_free(s);
}
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq)
{
mcf_fec_state *s;

6
hw/mcf_intc.c
View file

@ -41,7 +41,7 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -73,7 +73,7 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
}
}
static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
static void mcf_intc_write(void *opaque, a_target_phys_addr addr, uint32_t val)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@ -139,7 +139,7 @@ static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
mcf_intc_write
};
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env)
{
mcf_intc_state *s;
int iomemtype;

6
hw/mcf_uart.c
View file

@ -64,7 +64,7 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -182,7 +182,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@ -296,7 +296,7 @@ static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
mcf_uart_write
};
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;

14
hw/mips.h
View file

@ -6,19 +6,19 @@
PCIBus *pci_gt64120_init(qemu_irq *pic);
/* ds1225y.c */
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void *ds1225y_init(a_target_phys_addr mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
int g364fb_mm_init(a_target_phys_addr vram_base,
a_target_phys_addr ctrl_base, int it_shift,
qemu_irq irq);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
extern void jazz_led_init(target_phys_addr_t base);
extern void jazz_led_init(a_target_phys_addr base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);
@ -28,7 +28,7 @@ extern void cpu_mips_clock_init(CPUState *);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@ -36,8 +36,8 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
qemu_irq **irqs, rc4030_dma **dmas);
/* dp8393x.c */
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write));
#endif

16
hw/mips_jazz.c
View file

@ -47,12 +47,12 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
static uint32_t rtc_readb(void *opaque, a_target_phys_addr addr)
{
return cpu_inw(0x71);
}
static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void rtc_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
cpu_outw(0x71, val & 0xff);
}
@ -69,7 +69,7 @@ static CPUWriteMemoryFunc * const rtc_write[3] = {
rtc_writeb,
};
static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dma_dummy_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
@ -113,7 +113,7 @@ static void audio_init(qemu_irq *pic)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
void mips_jazz_init (ram_addr_t ram_size,
void mips_jazz_init (a_ram_addr ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@ -128,8 +128,8 @@ void mips_jazz_init (ram_addr_t ram_size,
PITState *pit;
BlockDriverState *fds[MAX_FD];
qemu_irq esp_reset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
/* init CPUs */
if (cpu_model == NULL) {
@ -271,7 +271,7 @@ void mips_jazz_init (ram_addr_t ram_size,
}
static
void mips_magnum_init (ram_addr_t ram_size,
void mips_magnum_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -280,7 +280,7 @@ void mips_magnum_init (ram_addr_t ram_size,
}
static
void mips_pica61_init (ram_addr_t ram_size,
void mips_pica61_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

24
hw/mips_malta.c
View file

@ -117,7 +117,7 @@ static void malta_fpga_update_display(void *opaque)
# define logout(fmt, ...) ((void)0)
#endif
struct _eeprom24c0x_t {
struct eeprom24c0x {
uint8_t tick;
uint8_t address;
uint8_t command;
@ -129,9 +129,9 @@ struct _eeprom24c0x_t {
uint8_t contents[256];
};
typedef struct _eeprom24c0x_t eeprom24c0x_t;
typedef struct eeprom24c0x a_eeprom24c0x;
static eeprom24c0x_t eeprom = {
static a_eeprom24c0x eeprom = {
.contents = {
/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
@ -217,7 +217,7 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@ -304,7 +304,7 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
static void malta_fpga_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
MaltaFPGAState *s = opaque;
@ -431,7 +431,7 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_printf(chr, "+--------+\r\n");
}
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
static MaltaFPGAState *malta_fpga_init(a_target_phys_addr base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
int malta;
@ -658,7 +658,7 @@ static void write_bootloader (CPUState *env, uint8_t *base,
static void prom_set(int index, const char *string, ...)
{
char buf[ENVP_ENTRY_SIZE];
target_phys_addr_t p;
a_target_phys_addr p;
va_list ap;
int32_t table_addr;
@ -688,7 +688,7 @@ static int64_t load_kernel (CPUState *env)
int64_t kernel_entry, kernel_low, kernel_high;
int index = 0;
long initrd_size;
ram_addr_t initrd_offset;
a_ram_addr initrd_offset;
int big_endian;
#ifdef TARGET_WORDS_BIGENDIAN
@ -763,21 +763,21 @@ static void main_cpu_reset(void *opaque)
}
static
void mips_malta_init (ram_addr_t ram_size,
void mips_malta_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
ISADevice *isa_dev;
CPUState *env;
RTCState *rtc_state;
fdctrl_t *floppy_controller;
a_fdctrl *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
int piix4_devfn;

8
hw/mips_mipssim.c
View file

@ -55,7 +55,7 @@ static void load_kernel (CPUState *env)
int64_t entry, kernel_low, kernel_high;
long kernel_size;
long initrd_size;
ram_addr_t initrd_offset;
a_ram_addr initrd_offset;
int big_endian;
#ifdef TARGET_WORDS_BIGENDIAN
@ -111,14 +111,14 @@ static void main_cpu_reset(void *opaque)
}
static void
mips_mipssim_init (ram_addr_t ram_size,
mips_mipssim_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
CPUState *env;
int bios_size;

12
hw/mips_r4k.c
View file

@ -45,7 +45,7 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
static void mips_qemu_writel (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
if ((addr & 0xffff) == 0 && val == 42)
@ -54,7 +54,7 @@ static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
qemu_system_shutdown_request ();
}
static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
static uint32_t mips_qemu_readl (void *opaque, a_target_phys_addr addr)
{
return 0;
}
@ -77,7 +77,7 @@ static void load_kernel (CPUState *env)
{
int64_t entry, kernel_low, kernel_high;
long kernel_size, initrd_size;
ram_addr_t initrd_offset;
a_ram_addr initrd_offset;
int ret;
int big_endian;
@ -151,14 +151,14 @@ static void main_cpu_reset(void *opaque)
static const int sector_len = 32 * 1024;
static
void mips_r4k_init (ram_addr_t ram_size,
void mips_r4k_init (a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
a_ram_addr ram_offset;
a_ram_addr bios_offset;
int bios_size;
CPUState *env;
RTCState *rtc_state;

6
hw/mpcore.c
View file

@ -155,7 +155,7 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
/* Per-CPU private memory mapped IO. */
static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
static uint32_t mpcore_priv_read(void *opaque, a_target_phys_addr offset)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@ -199,7 +199,7 @@ bad_reg:
return 0;
}
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
static void mpcore_priv_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@ -255,7 +255,7 @@ static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
mpcore_priv_write
};
static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
static void mpcore_priv_map(SysBusDevice *dev, a_target_phys_addr base)
{
mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
cpu_register_physical_memory(base, 0x1000, s->iomemtype);

10
hw/msix.c
View file

@ -123,7 +123,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
qemu_set_irq(dev->irq[0], 0);
}
static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
static uint32_t msix_mmio_readl(void *opaque, a_target_phys_addr addr)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (dev->msix_page_size - 1);
@ -135,7 +135,7 @@ static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
static uint32_t msix_mmio_read_unallowed(void *opaque, a_target_phys_addr addr)
{
fprintf(stderr, "MSI-X: only dword read is allowed!\n");
return 0;
@ -172,7 +172,7 @@ static int msix_is_masked(PCIDevice *dev, int vector)
return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
}
static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
static void msix_mmio_writel(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
PCIDevice *dev = opaque;
@ -185,7 +185,7 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
}
}
static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
static void msix_mmio_write_unallowed(void *opaque, a_target_phys_addr addr,
uint32_t val)
{
fprintf(stderr, "MSI-X: only dword write is allowed!\n");
@ -221,7 +221,7 @@ void msix_mmio_map(PCIDevice *d, int region_num,
/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
* modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size)
unsigned bar_nr, unsigned bar_size, a_target_phys_addr page_size)
{
int ret;
/* Nothing to do if MSI is not supported by interrupt controller */

2
hw/msix.h
View file

@ -5,7 +5,7 @@
int msix_init(struct PCIDevice *dev, unsigned short nentries,
unsigned bar_nr, unsigned bar_size,
target_phys_addr_t page_size);
a_target_phys_addr page_size);
void msix_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len);

4
hw/mst_fpga.c
View file

@ -78,7 +78,7 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
static uint32_t
mst_fpga_readb(void *opaque, target_phys_addr_t addr)
mst_fpga_readb(void *opaque, a_target_phys_addr addr)
{
mst_irq_state *s = (mst_irq_state *) opaque;
@ -115,7 +115,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
}
static void
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
mst_fpga_writeb(void *opaque, a_target_phys_addr addr, uint32_t value)
{
mst_irq_state *s = (mst_irq_state *) opaque;
value &= 0xffffffff;

36
hw/musicpal.c
View file

@ -255,7 +255,7 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
static uint32_t mv88w8618_eth_read(void *opaque, a_target_phys_addr offset)
{
mv88w8618_eth_state *s = opaque;
@ -296,7 +296,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
}
}
static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_eth_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mv88w8618_eth_state *s = opaque;
@ -481,7 +481,7 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
s->brightness |= level << irq;
}
static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
static uint32_t musicpal_lcd_read(void *opaque, a_target_phys_addr offset)
{
musicpal_lcd_state *s = opaque;
@ -494,7 +494,7 @@ static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
}
}
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
static void musicpal_lcd_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
musicpal_lcd_state *s = opaque;
@ -594,7 +594,7 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
mv88w8618_pic_update(s);
}
static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
static uint32_t mv88w8618_pic_read(void *opaque, a_target_phys_addr offset)
{
mv88w8618_pic_state *s = opaque;
@ -607,7 +607,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
}
}
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_pic_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mv88w8618_pic_state *s = opaque;
@ -705,7 +705,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
static uint32_t mv88w8618_pit_read(void *opaque, a_target_phys_addr offset)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@ -720,7 +720,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
}
}
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_pit_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mv88w8618_pit_state *s = opaque;
@ -792,7 +792,7 @@ typedef struct mv88w8618_flashcfg_state {
} mv88w8618_flashcfg_state;
static uint32_t mv88w8618_flashcfg_read(void *opaque,
target_phys_addr_t offset)
a_target_phys_addr offset)
{
mv88w8618_flashcfg_state *s = opaque;
@ -805,7 +805,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque,
}
}
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_flashcfg_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
mv88w8618_flashcfg_state *s = opaque;
@ -846,7 +846,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
#define MP_BOARD_REVISION 0x31
static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
static uint32_t musicpal_misc_read(void *opaque, a_target_phys_addr offset)
{
switch (offset) {
case MP_MISC_BOARD_REVISION:
@ -857,7 +857,7 @@ static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
}
}
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
static void musicpal_misc_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
}
@ -887,7 +887,7 @@ static void musicpal_misc_init(void)
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
static uint32_t mv88w8618_wlan_read(void *opaque, a_target_phys_addr offset)
{
switch (offset) {
/* Workaround to allow loading the binary-only wlandrv.ko crap
@ -902,7 +902,7 @@ static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
}
}
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
static void mv88w8618_wlan_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
}
@ -1049,7 +1049,7 @@ static void musicpal_gpio_irq(void *opaque, int irq, int level)
musicpal_gpio_keys_update(s);
}
static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
static uint32_t musicpal_gpio_read(void *opaque, a_target_phys_addr offset)
{
musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
@ -1080,7 +1080,7 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
}
}
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
static void musicpal_gpio_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
@ -1275,7 +1275,7 @@ static struct arm_boot_info musicpal_binfo = {
.board_id = 0x20e,
};
static void musicpal_init(ram_addr_t ram_size,
static void musicpal_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1295,7 +1295,7 @@ static void musicpal_init(ram_addr_t ram_size,
int i;
unsigned long flash_size;
DriveInfo *dinfo;
ram_addr_t sram_off;
a_ram_addr sram_off;
if (!cpu_model)
cpu_model = "arm926";

8
hw/nseries.c
View file

@ -1094,7 +1094,7 @@ static struct omap_partition_info_s {
{ 0, 0, 0, NULL }
};
static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
static a_bdaddr n8x0_bd_addr = {{ N8X0_BD_ADDR }};
static int n8x0_atag_setup(void *p, int model)
{
@ -1265,7 +1265,7 @@ static int n810_atag_setup(struct arm_boot_info *info, void *p)
return n8x0_atag_setup(p, 810);
}
static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
static void n8x0_init(a_ram_addr ram_size, const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model)
@ -1383,7 +1383,7 @@ static struct arm_boot_info n810_binfo = {
.atag_board = n810_atag_setup,
};
static void n800_init(ram_addr_t ram_size,
static void n800_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1393,7 +1393,7 @@ static void n800_init(ram_addr_t ram_size,
cpu_model, &n800_binfo, 800);
}
static void n810_init(ram_addr_t ram_size,
static void n810_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

38
hw/nvram.h
View file

@ -2,26 +2,26 @@
#define NVRAM_H
/* NVRAM helpers */
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
typedef struct nvram_t {
typedef uint32_t (*a_nvram_read)(void *private, uint32_t addr);
typedef void (*a_nvram_write)(void *private, uint32_t addr, uint32_t val);
typedef struct nvram {
void *opaque;
nvram_read_t read_fn;
nvram_write_t write_fn;
} nvram_t;
a_nvram_read read_fn;
a_nvram_write write_fn;
} a_nvram;
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value);
uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr);
void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value);
uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr);
void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value);
uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr);
void NVRAM_set_string (a_nvram *nvram, uint32_t addr,
const char *str, uint32_t max);
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max);
void NVRAM_set_crc (a_nvram *nvram, uint32_t addr,
uint32_t start, uint32_t count);
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size,
const char *arch,
uint32_t RAM_size, int boot_device,
uint32_t kernel_image, uint32_t kernel_size,
@ -29,13 +29,13 @@ int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
uint32_t initrd_image, uint32_t initrd_size,
uint32_t NVRAM_image,
int width, int height, int depth);
typedef struct m48t59_t m48t59_t;
typedef struct m48t59 a_m48t59;
void m48t59_write (void *private, uint32_t addr, uint32_t val);
uint32_t m48t59_read (void *private, uint32_t addr);
void m48t59_toggle_lock (void *private, int lock);
m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
uint32_t io_base, uint16_t size,
int type);
void m48t59_set_addr (void *opaque, uint32_t addr);

96
hw/omap.h
View file

@ -63,19 +63,19 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* omap[123].c */
struct omap_l4_s;
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype);
# define l4_register_io_memory cpu_register_io_memory
struct omap_intr_handler_s;
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base,
unsigned long size, unsigned char nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base,
int size, int nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq,
omap_clk fclk, omap_clk iclk);
@ -91,12 +91,12 @@ struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu);
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*base_upd)(void *opaque, a_target_phys_addr new),
void (*unmap)(void *opaque), void *opaque);
/*
@ -416,10 +416,10 @@ enum omap_dma_model {
};
struct soc_dma_s;
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct soc_dma_s *s);
@ -445,15 +445,15 @@ typedef enum {
post_incremented,
single_index,
double_index,
} omap_dma_addressing_t;
} e_omap_dma_addressing;
/* Only used in OMAP DMA 3.x gigacells */
struct omap_dma_lcd_channel_s {
enum omap_dma_port src;
target_phys_addr_t src_f1_top;
target_phys_addr_t src_f1_bottom;
target_phys_addr_t src_f2_top;
target_phys_addr_t src_f2_bottom;
a_target_phys_addr src_f1_top;
a_target_phys_addr src_f1_bottom;
a_target_phys_addr src_f2_top;
a_target_phys_addr src_f2_bottom;
/* Used in OMAP DMA 3.2 gigacell */
unsigned char brust_f1;
@ -480,8 +480,8 @@ struct omap_dma_lcd_channel_s {
uint16_t frames_f1;
uint16_t elements_f2;
uint16_t frames_f2;
omap_dma_addressing_t mode_f1;
omap_dma_addressing_t mode_f2;
e_omap_dma_addressing mode_f1;
e_omap_dma_addressing mode_f2;
/* Destination port is fixed. */
int interrupts;
@ -489,7 +489,7 @@ struct omap_dma_lcd_channel_s {
int dual;
int current_frame;
target_phys_addr_t phys_framebuffer[2];
a_target_phys_addr phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
@ -628,7 +628,7 @@ struct omap_dma_lcd_channel_s {
/* omap[123].c */
struct omap_mpu_timer_s;
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk);
struct omap_gp_timer_s;
@ -636,22 +636,22 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk);
struct omap_watchdog_timer_s;
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk);
struct omap_32khz_timer_s;
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk);
void omap_synctimer_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
struct omap_tipb_bridge_s;
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base,
qemu_irq abort_irq, omap_clk clk);
struct omap_uart_s;
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
struct omap_uart_s *omap_uart_init(a_target_phys_addr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
@ -661,7 +661,7 @@ void omap_uart_reset(struct omap_uart_s *s);
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
struct omap_mpuio_s;
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk);
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
@ -669,7 +669,7 @@ void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
struct omap_gpio_s;
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk);
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
@ -686,7 +686,7 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base,
qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@ -699,7 +699,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
int chipselect);
struct omap_rtc_s;
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base,
qemu_irq *irq, omap_clk clk);
struct I2SCodec {
@ -727,12 +727,12 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
struct omap_lpg_s;
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk);
void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu);
@ -744,9 +744,9 @@ struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
/* omap_lcdc.c */
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
@ -758,7 +758,7 @@ struct rfbi_chip_s {
struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
target_phys_addr_t l3_base,
a_target_phys_addr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
@ -766,7 +766,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
/* omap_mmc.c */
struct omap_mmc_s;
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
@ -778,7 +778,7 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base,
qemu_irq irq, qemu_irq *dma, omap_clk clk);
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
@ -829,11 +829,11 @@ struct omap_mpu_state_s {
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset);
a_target_phys_addr offset);
void (*write[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset, uint32_t value);
a_target_phys_addr offset, uint32_t value);
int (*addr_valid)(struct omap_mpu_state_s *s,
target_phys_addr_t addr);
a_target_phys_addr addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
@ -969,14 +969,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
# error TARGET_PHYS_ADDR_BITS undefined
# endif
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr);
void omap_badwidth_write8(void *opaque, a_target_phys_addr addr,
uint32_t value);
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr);
void omap_badwidth_write16(void *opaque, a_target_phys_addr addr,
uint32_t value);
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr);
void omap_badwidth_write32(void *opaque, a_target_phys_addr addr,
uint32_t value);
void omap_mpu_wakeup(void *opaque, int irq, int req);
@ -1045,7 +1045,7 @@ struct io_fn {
int in;
};
static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
static uint32_t io_readb(void *opaque, a_target_phys_addr addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@ -1057,7 +1057,7 @@ static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
return ret;
}
static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
static uint32_t io_readh(void *opaque, a_target_phys_addr addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@ -1069,7 +1069,7 @@ static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
return ret;
}
static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
static uint32_t io_readw(void *opaque, a_target_phys_addr addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@ -1081,7 +1081,7 @@ static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
return ret;
}
static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
static void io_writeb(void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct io_fn *s = opaque;
@ -1091,7 +1091,7 @@ static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
s->mem_write[0](s->opaque, addr, value);
s->in --;
}
static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
static void io_writeh(void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct io_fn *s = opaque;
@ -1101,7 +1101,7 @@ static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
s->mem_write[1](s->opaque, addr, value);
s->in --;
}
static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
static void io_writew(void *opaque, a_target_phys_addr addr, uint32_t value)
{
struct io_fn *s = opaque;

174
hw/omap1.c
View file

@ -27,7 +27,7 @@
#include "pc.h"
/* Should signal the TCMI/GPMC */
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr)
{
uint8_t ret;
@ -36,7 +36,7 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
return ret;
}
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
void omap_badwidth_write8(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
uint8_t val8 = value;
@ -45,7 +45,7 @@ void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr)
{
uint16_t ret;
@ -54,7 +54,7 @@ uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
return ret;
}
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
void omap_badwidth_write16(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
uint16_t val16 = value;
@ -63,7 +63,7 @@ void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr)
{
uint32_t ret;
@ -72,7 +72,7 @@ uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
return ret;
}
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
void omap_badwidth_write32(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
OMAP_32B_REG(addr);
@ -196,7 +196,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_inth_read(void *opaque, a_target_phys_addr addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@ -273,7 +273,7 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_inth_write(void *opaque, target_phys_addr_t addr,
static void omap_inth_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@ -406,7 +406,7 @@ void omap_inth_reset(struct omap_intr_handler_s *s)
qemu_set_irq(s->parent_intr[1], 0);
}
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base,
unsigned long size, unsigned char nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
{
@ -431,7 +431,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
return s;
}
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap2_inth_read(void *opaque, a_target_phys_addr addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@ -508,7 +508,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
static void omap2_inth_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@ -624,7 +624,7 @@ static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
omap2_inth_write,
};
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base,
int size, int nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq,
omap_clk fclk, omap_clk iclk)
@ -748,7 +748,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
timer->rate = omap_clk_getrate(timer->clk);
}
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mpu_timer_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@ -767,7 +767,7 @@ static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
static void omap_mpu_timer_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@ -819,7 +819,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
s->it_ena = 1;
}
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@ -849,7 +849,7 @@ struct omap_watchdog_timer_s {
int reset;
};
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_wd_timer_read(void *opaque, a_target_phys_addr addr)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@ -869,7 +869,7 @@ static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
static void omap_wd_timer_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@ -943,7 +943,7 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
omap_timer_update(&s->timer);
}
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@ -968,7 +968,7 @@ struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer;
};
static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_os_timer_read(void *opaque, a_target_phys_addr addr)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -990,7 +990,7 @@ static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
static void omap_os_timer_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@ -1045,7 +1045,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
s->timer.ar = 1;
}
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@ -1066,7 +1066,7 @@ struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
}
/* Ultra Low-Power Device Module */
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_ulpd_pm_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret;
@ -1128,7 +1128,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
static void omap_ulpd_pm_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1282,7 +1282,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
}
static void omap_ulpd_pm_init(target_phys_addr_t base,
static void omap_ulpd_pm_init(a_target_phys_addr base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
@ -1293,7 +1293,7 @@ static void omap_ulpd_pm_init(target_phys_addr_t base,
}
/* OMAP Pin Configuration */
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_pin_cfg_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1395,7 +1395,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
static void omap_pin_cfg_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1497,7 +1497,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
}
static void omap_pin_cfg_init(target_phys_addr_t base,
static void omap_pin_cfg_init(a_target_phys_addr base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
@ -1508,7 +1508,7 @@ static void omap_pin_cfg_init(target_phys_addr_t base,
}
/* Device Identification, Die Identification */
static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_id_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1550,7 +1550,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_id_write(void *opaque, target_phys_addr_t addr,
static void omap_id_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@ -1579,7 +1579,7 @@ static void omap_id_init(struct omap_mpu_state_s *mpu)
}
/* MPUI Control (Dummy) */
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mpui_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1607,7 +1607,7 @@ static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
static void omap_mpui_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1650,7 +1650,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b;
}
static void omap_mpui_init(target_phys_addr_t base,
static void omap_mpui_init(a_target_phys_addr base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
@ -1672,7 +1672,7 @@ struct omap_tipb_bridge_s {
uint16_t enh_control;
};
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_tipb_bridge_read(void *opaque, a_target_phys_addr addr)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@ -1697,7 +1697,7 @@ static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
static void omap_tipb_bridge_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@ -1752,7 +1752,7 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
s->enh_control = 0x000f;
}
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base,
qemu_irq abort_irq, omap_clk clk)
{
int iomemtype;
@ -1770,7 +1770,7 @@ struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
}
/* Dummy Traffic Controller's Memory Interface */
static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_tcmi_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
@ -1803,7 +1803,7 @@ static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
static void omap_tcmi_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -1865,7 +1865,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
static void omap_tcmi_init(target_phys_addr_t base,
static void omap_tcmi_init(a_target_phys_addr base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
@ -1876,7 +1876,7 @@ static void omap_tcmi_init(target_phys_addr_t base,
}
/* Digital phase-locked loops control */
static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_dpll_read(void *opaque, a_target_phys_addr addr)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@ -1887,7 +1887,7 @@ static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
static void omap_dpll_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@ -1938,7 +1938,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
omap_clk_setrate(s->dpll, 1, 1);
}
static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
static void omap_dpll_init(struct dpll_ctl_s *s, a_target_phys_addr base,
omap_clk clk)
{
int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
@ -1952,7 +1952,7 @@ static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
/* UARTs */
struct omap_uart_s {
target_phys_addr_t base;
a_target_phys_addr base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
@ -1976,7 +1976,7 @@ void omap_uart_reset(struct omap_uart_s *s)
s->clksel = 0;
}
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
struct omap_uart_s *omap_uart_init(a_target_phys_addr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
@ -1992,7 +1992,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
return s;
}
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_uart_read(void *opaque, a_target_phys_addr addr)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@ -2026,7 +2026,7 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_uart_write(void *opaque, target_phys_addr_t addr,
static void omap_uart_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@ -2085,7 +2085,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
a_target_phys_addr base = omap_l4_attach(ta, 0, 0);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
@ -2107,7 +2107,7 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
}
/* MPU Clock/Reset/Power Mode Control */
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_clkm_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -2303,7 +2303,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
}
}
static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
static void omap_clkm_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -2393,7 +2393,7 @@ static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
omap_badwidth_write16,
};
static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_clkdsp_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -2432,7 +2432,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
static void omap_clkdsp_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -2499,8 +2499,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
static void omap_clkm_init(target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
static void omap_clkm_init(a_target_phys_addr mpu_base,
a_target_phys_addr dsp_base, struct omap_mpu_state_s *s)
{
int iomemtype[2] = {
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
@ -2578,7 +2578,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
s->row_latch = ~rows;
}
static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mpuio_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -2633,7 +2633,7 @@ static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
static void omap_mpuio_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@ -2743,7 +2743,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int on)
omap_mpuio_kbd_update(s);
}
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
@ -2823,7 +2823,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
}
}
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gpio_read(void *opaque, a_target_phys_addr addr)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -2856,7 +2856,7 @@ static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
static void omap_gpio_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@ -2942,7 +2942,7 @@ static void omap_gpio_reset(struct omap_gpio_s *s)
s->pins = ~0;
}
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@ -3011,7 +3011,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
}
}
static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_uwire_read(void *opaque, a_target_phys_addr addr)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -3040,7 +3040,7 @@ static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
static void omap_uwire_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@ -3111,7 +3111,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base,
qemu_irq *irq, qemu_irq dma, omap_clk clk)
{
int iomemtype;
@ -3152,7 +3152,7 @@ static void omap_pwl_update(struct omap_mpu_state_s *s)
}
}
static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_pwl_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -3167,7 +3167,7 @@ static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
static void omap_pwl_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -3217,7 +3217,7 @@ static void omap_pwl_clk_update(void *opaque, int line, int on)
omap_pwl_update(s);
}
static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
static void omap_pwl_init(a_target_phys_addr base, struct omap_mpu_state_s *s,
omap_clk clk)
{
int iomemtype;
@ -3232,7 +3232,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
}
/* Pulse-Width Tone module */
static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_pwt_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -3249,7 +3249,7 @@ static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
static void omap_pwt_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -3311,7 +3311,7 @@ static void omap_pwt_reset(struct omap_mpu_state_s *s)
s->pwt.gcr = 0;
}
static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
static void omap_pwt_init(a_target_phys_addr base, struct omap_mpu_state_s *s,
omap_clk clk)
{
int iomemtype;
@ -3368,7 +3368,7 @@ static inline int omap_rtc_bin(uint8_t num)
return (num & 15) + 10 * (num >> 4);
}
static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_rtc_read(void *opaque, a_target_phys_addr addr)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -3445,7 +3445,7 @@ static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
static void omap_rtc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@ -3729,7 +3729,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
omap_rtc_tick(s);
}
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base,
qemu_irq *irq, omap_clk clk)
{
int iomemtype;
@ -3956,7 +3956,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
omap_mcbsp_rx_stop(s);
}
static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mcbsp_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -4049,7 +4049,7 @@ static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
static void omap_mcbsp_writeh(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@ -4187,7 +4187,7 @@ static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
static void omap_mcbsp_writew(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@ -4249,7 +4249,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk)
{
int iomemtype;
@ -4364,7 +4364,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_lpg_read(void *opaque, a_target_phys_addr addr)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -4381,7 +4381,7 @@ static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
static void omap_lpg_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@ -4426,7 +4426,7 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
omap_lpg_update(s);
}
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk)
{
int iomemtype;
struct omap_lpg_s *s = (struct omap_lpg_s *)
@ -4446,7 +4446,7 @@ struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
}
/* MPUI Peripheral Bridge configuration */
static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mpui_io_read(void *opaque, a_target_phys_addr addr)
{
if (addr == OMAP_MPUI_BASE) /* CMR */
return 0xfe4d;
@ -4517,8 +4517,8 @@ static void omap1_mpu_reset(void *opaque)
}
static const struct omap_map_s {
target_phys_addr_t phys_dsp;
target_phys_addr_t phys_mpu;
a_target_phys_addr phys_dsp;
a_target_phys_addr phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
@ -4586,37 +4586,37 @@ static const struct dma_irq_map omap1_dma_irq_map[] = {
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= 0xfffb0000 && addr < 0xffff0000;
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return addr >= 0xe1010000 && addr < 0xe1020004;
}
@ -4627,7 +4627,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
ram_addr_t imif_base, emiff_base;
a_ram_addr imif_base, emiff_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;

110
hw/omap2.c
View file

@ -263,7 +263,7 @@ static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
omap_gp_timer_update(s);
}
static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gp_timer_readw(void *opaque, a_target_phys_addr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@ -329,7 +329,7 @@ static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
return 0;
}
static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gp_timer_readh(void *opaque, a_target_phys_addr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
uint32_t ret;
@ -349,7 +349,7 @@ static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = {
omap_gp_timer_readw,
};
static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
static void omap_gp_timer_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@ -449,7 +449,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
}
}
static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
static void omap_gp_timer_writeh(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@ -499,7 +499,7 @@ static void omap_synctimer_reset(struct omap_synctimer_s *s)
s->val = omap_synctimer_read(s);
}
static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
static uint32_t omap_synctimer_readw(void *opaque, a_target_phys_addr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
@ -515,7 +515,7 @@ static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
return 0;
}
static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
static uint32_t omap_synctimer_readh(void *opaque, a_target_phys_addr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
uint32_t ret;
@ -535,7 +535,7 @@ static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
omap_synctimer_readw,
};
static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
static void omap_synctimer_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@ -658,7 +658,7 @@ static void omap_gpio_module_reset(struct omap2_gpio_s *s)
s->delay = 0;
}
static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gpio_module_read(void *opaque, a_target_phys_addr addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@ -730,7 +730,7 @@ static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
static void omap_gpio_module_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@ -872,12 +872,12 @@ static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
}
}
static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gpio_module_readp(void *opaque, a_target_phys_addr addr)
{
return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
}
static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
static void omap_gpio_module_writep(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
uint32_t cur = 0;
@ -975,7 +975,7 @@ static void omap_gpif_reset(struct omap_gpif_s *s)
s->gpo = 0;
}
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gpif_top_read(void *opaque, a_target_phys_addr addr)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
@ -1003,7 +1003,7 @@ static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
static void omap_gpif_top_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
@ -1187,7 +1187,7 @@ static void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_mcspi_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
@ -1256,7 +1256,7 @@ static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
static void omap_mcspi_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
@ -1696,7 +1696,7 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_eac_read(void *opaque, a_target_phys_addr addr)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
uint32_t ret;
@ -1807,7 +1807,7 @@ static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_eac_write(void *opaque, target_phys_addr_t addr,
static void omap_eac_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@ -2014,7 +2014,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
omap_sti_interrupt_update(s);
}
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_sti_read(void *opaque, a_target_phys_addr addr)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@ -2050,7 +2050,7 @@ static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_sti_write(void *opaque, target_phys_addr_t addr,
static void omap_sti_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@ -2108,13 +2108,13 @@ static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
omap_sti_write,
};
static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_sti_fifo_read(void *opaque, a_target_phys_addr addr)
{
OMAP_BAD_REG(addr);
return 0;
}
static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
static void omap_sti_fifo_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@ -2147,7 +2147,7 @@ static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
a_target_phys_addr channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
int iomemtype;
@ -2175,14 +2175,14 @@ struct omap_target_agent_s {
struct omap_l4_s *bus;
int regions;
struct omap_l4_region_s *start;
target_phys_addr_t base;
a_target_phys_addr base;
uint32_t component;
uint32_t control;
uint32_t status;
};
struct omap_l4_s {
target_phys_addr_t base;
a_target_phys_addr base;
int ta_num;
struct omap_target_agent_s ta[0];
};
@ -2213,28 +2213,28 @@ int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
return omap_l4_io_entries ++;
}
static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
static uint32_t omap_l4_io_readb(void *opaque, a_target_phys_addr addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
}
static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
static uint32_t omap_l4_io_readh(void *opaque, a_target_phys_addr addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
}
static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
static uint32_t omap_l4_io_readw(void *opaque, a_target_phys_addr addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
}
static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
static void omap_l4_io_writeb(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@ -2242,7 +2242,7 @@ static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
}
static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
static void omap_l4_io_writeh(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@ -2250,7 +2250,7 @@ static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
}
static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
static void omap_l4_io_writew(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@ -2271,7 +2271,7 @@ static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
};
#endif
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num)
{
struct omap_l4_s *bus = qemu_mallocz(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
@ -2299,7 +2299,7 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
return bus;
}
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_l4ta_read(void *opaque, a_target_phys_addr addr)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@ -2318,7 +2318,7 @@ static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
static void omap_l4ta_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@ -2356,7 +2356,7 @@ static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
#define L4TAO(n) ((n) + 39)
static struct omap_l4_region_s {
target_phys_addr_t offset;
a_target_phys_addr offset;
size_t size;
int access;
} omap_l4_region[125] = {
@ -2584,10 +2584,10 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
return ta;
}
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype)
{
target_phys_addr_t base;
a_target_phys_addr base;
ssize_t size;
#ifdef L4_MUX_HACK
int i;
@ -2622,7 +2622,7 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
}
/* TEST-Chip-level TAP */
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_tap_read(void *opaque, a_target_phys_addr addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@ -2686,7 +2686,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_tap_write(void *opaque, target_phys_addr_t addr,
static void omap_tap_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@ -2753,7 +2753,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_prcm_read(void *opaque, a_target_phys_addr addr)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
uint32_t ret;
@ -3060,7 +3060,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
}
}
static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
static void omap_prcm_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@ -3540,7 +3540,7 @@ struct omap_sysctl_s {
uint32_t msuspendmux[5];
};
static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
static uint32_t omap_sysctl_read8(void *opaque, a_target_phys_addr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@ -3565,7 +3565,7 @@ static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
return 0;
}
static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_sysctl_read(void *opaque, a_target_phys_addr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@ -3665,7 +3665,7 @@ static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
static void omap_sysctl_write8(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@ -3689,7 +3689,7 @@ static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
}
}
static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
static void omap_sysctl_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@ -3907,7 +3907,7 @@ static void omap_sdrc_reset(struct omap_sdrc_s *s)
s->config = 0x10;
}
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_sdrc_read(void *opaque, a_target_phys_addr addr)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@ -3957,7 +3957,7 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
static void omap_sdrc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@ -4026,7 +4026,7 @@ static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
omap_sdrc_write,
};
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base)
{
int iomemtype;
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
@ -4056,10 +4056,10 @@ struct omap_gpmc_s {
int prefcount;
struct omap_gpmc_cs_file_s {
uint32_t config[7];
target_phys_addr_t base;
a_target_phys_addr base;
size_t size;
int iomemtype;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*base_update)(void *opaque, a_target_phys_addr new);
void (*unmap)(void *opaque);
void *opaque;
} cs_file[8];
@ -4151,7 +4151,7 @@ static void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_gpmc_read(void *opaque, a_target_phys_addr addr)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@ -4248,7 +4248,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
static void omap_gpmc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@ -4400,7 +4400,7 @@ static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
omap_gpmc_write,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq)
{
int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
@ -4416,7 +4416,7 @@ struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
}
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*base_upd)(void *opaque, a_target_phys_addr new),
void (*unmap)(void *opaque), void *opaque)
{
struct omap_gpmc_cs_file_s *f;
@ -4475,7 +4475,7 @@ static void omap2_mpu_reset(void *opaque)
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
a_target_phys_addr addr)
{
return 1;
}
@ -4492,7 +4492,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
ram_addr_t sram_base, q2_base;
a_ram_addr sram_base, q2_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[4];
omap_clk gpio_clks[4];

34
hw/omap_dma.c
View file

@ -31,8 +31,8 @@ struct omap_dma_channel_s {
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
target_phys_addr_t addr[2];
omap_dma_addressing_t mode[2];
a_target_phys_addr addr[2];
e_omap_dma_addressing mode[2];
uint32_t elements;
uint16_t frames;
int32_t frame_index[2];
@ -78,7 +78,7 @@ struct omap_dma_channel_s {
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
target_phys_addr_t src, dest;
a_target_phys_addr src, dest;
int frame;
int element;
int pck_element;
@ -885,8 +885,8 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x02: /* SYS_DMA_CCR_CH0 */
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
ch->end_prog = (value & 0x0800) >> 11;
if (s->model >= omap_dma_3_2)
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
@ -911,7 +911,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
OMAP_RO_REG((target_phys_addr_t) reg);
OMAP_RO_REG((a_target_phys_addr) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
@ -951,7 +951,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
OMAP_RO_REG((target_phys_addr_t) reg);
OMAP_RO_REG((a_target_phys_addr) reg);
break;
case 0x1c: /* DMA_CDEI */
@ -1443,7 +1443,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
return 0;
}
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_dma_read(void *opaque, a_target_phys_addr addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
@ -1486,7 +1486,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_dma_write(void *opaque, target_phys_addr_t addr,
static void omap_dma_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1612,7 +1612,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
}
}
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
{
@ -1686,7 +1686,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
qemu_irq_raise(s->irq[3]);
}
static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_dma4_read(void *opaque, a_target_phys_addr addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int irqn = 0, chnum;
@ -1831,7 +1831,7 @@ static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
}
}
static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
static void omap_dma4_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1908,8 +1908,8 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
ch->bs = (value >> 18) & 1;
ch->transparent_copy = (value >> 17) & 1;
ch->constant_fill = (value >> 16) & 1;
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
ch->suspend = (value & 0x0100) >> 8;
ch->priority = (value & 0x0040) >> 6;
ch->fs = (value & 0x0020) >> 5;
@ -1973,12 +1973,12 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
break;
case 0x1c: /* DMA4_CSSA */
ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
ch->addr[0] = (a_target_phys_addr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
ch->addr[1] = (a_target_phys_addr) (uint32_t) value;
ch->set_update = 1;
break;
@ -2031,7 +2031,7 @@ static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
omap_dma4_write,
};
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
{

36
hw/omap_dss.c
View file

@ -59,7 +59,7 @@ struct omap_dss_s {
int nx;
int ny;
target_phys_addr_t addr[3];
a_target_phys_addr addr[3];
uint32_t attr;
uint32_t tresh;
@ -167,7 +167,7 @@ void omap_dss_reset(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -200,7 +200,7 @@ static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_diss_write(void *opaque, target_phys_addr_t addr,
static void omap_diss_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -242,7 +242,7 @@ static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
omap_diss_write,
};
static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -362,7 +362,7 @@ static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_disc_write(void *opaque, target_phys_addr_t addr,
static void omap_disc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -488,11 +488,11 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
s->dispc.l[0].addr[0] = (a_target_phys_addr) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
s->dispc.l[0].addr[1] = (a_target_phys_addr) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
@ -529,7 +529,7 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
s->dispc.l[0].addr[2] = (a_target_phys_addr) value;
s->dispc.invalidate = 1;
break;
@ -594,11 +594,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
target_phys_addr_t len;
target_phys_addr_t data_addr;
a_target_phys_addr len;
a_target_phys_addr data_addr;
int pitch;
static void *bounce_buffer;
static target_phys_addr_t bounce_len;
static a_target_phys_addr bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
@ -655,7 +655,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -717,7 +717,7 @@ static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
static void omap_rfbi_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@ -853,7 +853,7 @@ static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
omap_rfbi_write,
};
static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
{
switch (addr) {
case 0x00: /* REV_ID */
@ -908,7 +908,7 @@ static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_venc_write(void *opaque, target_phys_addr_t addr,
static void omap_venc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
switch (addr) {
@ -972,7 +972,7 @@ static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
omap_venc_write,
};
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
{
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
@ -993,7 +993,7 @@ static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_im3_write(void *opaque, target_phys_addr_t addr,
static void omap_im3_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
switch (addr) {
@ -1023,7 +1023,7 @@ static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
target_phys_addr_t l3_base,
a_target_phys_addr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)

8
hw/omap_i2c.c
View file

@ -140,7 +140,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
s->test = 0;
}
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_i2c_read(void *opaque, a_target_phys_addr addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@ -238,7 +238,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
static void omap_i2c_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@ -380,7 +380,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
}
}
static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
static void omap_i2c_writeb(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@ -420,7 +420,7 @@ static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
omap_badwidth_write16,
};
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base,
qemu_irq irq, qemu_irq *dma, omap_clk clk)
{
int iomemtype;

14
hw/omap_lcdc.c
View file

@ -24,8 +24,8 @@
struct omap_lcd_panel_s {
qemu_irq irq;
DisplayState *state;
ram_addr_t imif_base;
ram_addr_t emiff_base;
a_ram_addr imif_base;
a_ram_addr emiff_base;
int plm;
int tft;
@ -117,7 +117,7 @@ static void omap_update_display(void *opaque)
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
target_phys_addr_t frame_base;
a_target_phys_addr frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
@ -325,7 +325,7 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
static uint32_t omap_lcdc_read(void *opaque, a_target_phys_addr addr)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@ -357,7 +357,7 @@ static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
static void omap_lcdc_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@ -435,9 +435,9 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
s->ctrl = 0;
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)

14
hw/omap_mmc.c
View file

@ -104,10 +104,10 @@ typedef enum {
sd_r3, /* OCR register */
sd_r6 = 6, /* Published RCA response */
sd_r1b = -1,
} sd_rsp_type_t;
} e_sd_rsp_type;
static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
e_sd_cmd_type type, int busy, e_sd_rsp_type resptype, int init)
{
uint32_t rspstatus, mask;
int rsplen, timeout;
@ -305,7 +305,7 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->clkdiv = 0;
}
static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
static uint32_t omap_mmc_read(void *opaque, a_target_phys_addr offset)
{
uint16_t i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
@ -394,7 +394,7 @@ static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
return 0;
}
static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
static void omap_mmc_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
int i;
@ -410,9 +410,9 @@ static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
for (i = 0; i < 8; i ++)
s->rsp[i] = 0x0000;
omap_mmc_command(s, value & 63, (value >> 15) & 1,
(sd_cmd_type_t) ((value >> 12) & 3),
(e_sd_cmd_type) ((value >> 12) & 3),
(value >> 11) & 1,
(sd_rsp_type_t) ((value >> 8) & 7),
(e_sd_rsp_type) ((value >> 8) & 7),
(value >> 7) & 1);
omap_mmc_update(s);
break;
@ -569,7 +569,7 @@ static void omap_mmc_cover_cb(void *opaque, int line, int level)
}
}
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
{

16
hw/omap_sx1.c
View file

@ -58,28 +58,28 @@
* - 1 RTC
*/
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
static uint32_t static_readb(void *opaque, a_target_phys_addr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
static uint32_t static_readh(void *opaque, a_target_phys_addr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
static uint32_t static_readw(void *opaque, a_target_phys_addr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
static void static_write(void *opaque, target_phys_addr_t offset,
static void static_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
#ifdef SPY
@ -114,7 +114,7 @@ static struct arm_boot_info sx1_binfo = {
.board_id = 0x265,
};
static void sx1_init(ram_addr_t ram_size,
static void sx1_init(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
@ -126,7 +126,7 @@ static void sx1_init(ram_addr_t ram_size,
static uint32_t cs1val = 0x00215070;
static uint32_t cs2val = 0x00001139;
static uint32_t cs3val = 0x00001139;
ram_addr_t phys_flash;
a_ram_addr phys_flash;
DriveInfo *dinfo;
int fl_idx;
uint32_t flash_size = flash0_size;
@ -204,7 +204,7 @@ static void sx1_init(ram_addr_t ram_size,
//~ qemu_console_resize(ds, 640, 480);
}
static void sx1_init_v1(ram_addr_t ram_size,
static void sx1_init_v1(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -213,7 +213,7 @@ static void sx1_init_v1(ram_addr_t ram_size,
kernel_cmdline, initrd_filename, cpu_model, 1);
}
static void sx1_init_v2(ram_addr_t ram_size,
static void sx1_init_v2(a_ram_addr ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

10
hw/onenand.c
View file

@ -33,7 +33,7 @@
typedef struct {
uint32_t id;
int shift;
target_phys_addr_t base;
a_target_phys_addr base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
@ -41,7 +41,7 @@ typedef struct {
uint8_t *image;
uint8_t *otp;
uint8_t *current;
ram_addr_t ram;
a_ram_addr ram;
uint8_t *boot[2];
uint8_t *data[2][2];
int iomemtype;
@ -96,7 +96,7 @@ enum {
ONEN_LOCK_UNLOCKED = 1 << 2,
};
void onenand_base_update(void *opaque, target_phys_addr_t new)
void onenand_base_update(void *opaque, a_target_phys_addr new)
{
OneNANDState *s = (OneNANDState *) opaque;
@ -443,7 +443,7 @@ static void onenand_command(OneNANDState *s, int cmd)
onenand_intr_update(s);
}
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
static uint32_t onenand_read(void *opaque, a_target_phys_addr addr)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@ -507,7 +507,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
return 0;
}
static void onenand_write(void *opaque, target_phys_addr_t addr,
static void onenand_write(void *opaque, a_target_phys_addr addr,
uint32_t value)
{
OneNANDState *s = (OneNANDState *) opaque;

192
hw/openpic.c
View file

@ -166,19 +166,19 @@ enum {
IRQ_SPECIAL = 0x08,
};
typedef struct IRQ_queue_t {
typedef struct IRQ_queue {
uint32_t queue[BF_WIDTH(MAX_IRQ)];
int next;
int priority;
} IRQ_queue_t;
} a_IRQ_queue;
typedef struct IRQ_src_t {
typedef struct IRQ_src {
uint32_t ipvp; /* IRQ vector/priority register */
uint32_t ide; /* IRQ destination register */
int type;
int last_cpu;
int pending; /* TRUE if IRQ is pending */
} IRQ_src_t;
} a_IRQ_src;
enum IPVP_bits {
IPVP_MASK = 31,
@ -192,16 +192,16 @@ enum IPVP_bits {
#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
typedef struct IRQ_dst_t {
typedef struct IRQ_dst {
uint32_t tfrr;
uint32_t pctp; /* CPU current task priority */
uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
IRQ_queue_t servicing;
a_IRQ_queue raised;
a_IRQ_queue servicing;
qemu_irq *irqs;
} IRQ_dst_t;
} a_IRQ_dst;
typedef struct openpic_t {
typedef struct openpic {
PCIDevice pci_dev;
int mem_index;
/* Global registers */
@ -213,9 +213,9 @@ typedef struct openpic_t {
uint32_t spve; /* Spurious vector register */
uint32_t tifr; /* Timer frequency reporting register */
/* Source registers */
IRQ_src_t src[MAX_IRQ];
a_IRQ_src src[MAX_IRQ];
/* Local registers per output pin */
IRQ_dst_t dst[MAX_CPU];
a_IRQ_dst dst[MAX_CPU];
int nb_cpus;
/* Timer registers */
struct {
@ -242,10 +242,10 @@ typedef struct openpic_t {
int irq_tim0;
int need_swap;
void (*reset) (void *);
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
void (*irq_raise) (struct openpic *, int, a_IRQ_src *);
} a_openpic;
static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
static inline uint32_t openpic_swap32(a_openpic *opp, uint32_t val)
{
if (opp->need_swap)
return bswap32(val);
@ -253,22 +253,22 @@ static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
return val;
}
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
static inline void IRQ_setbit (a_IRQ_queue *q, int n_IRQ)
{
set_bit(q->queue, n_IRQ);
}
static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
static inline void IRQ_resetbit (a_IRQ_queue *q, int n_IRQ)
{
reset_bit(q->queue, n_IRQ);
}
static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
static inline int IRQ_testbit (a_IRQ_queue *q, int n_IRQ)
{
return test_bit(q->queue, n_IRQ);
}
static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
static void IRQ_check (a_openpic *opp, a_IRQ_queue *q)
{
int next, i;
int priority;
@ -289,7 +289,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
q->priority = priority;
}
static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
static int IRQ_get_next (a_openpic *opp, a_IRQ_queue *q)
{
if (q->next == -1) {
/* XXX: optimize */
@ -299,10 +299,10 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
return q->next;
}
static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
static void IRQ_local_pipe (a_openpic *opp, int n_CPU, int n_IRQ)
{
IRQ_dst_t *dst;
IRQ_src_t *src;
a_IRQ_dst *dst;
a_IRQ_src *src;
int priority;
dst = &opp->dst[n_CPU];
@ -341,9 +341,9 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
}
/* update pic state because registers for n_IRQ have changed value */
static void openpic_update_irq(openpic_t *opp, int n_IRQ)
static void openpic_update_irq(a_openpic *opp, int n_IRQ)
{
IRQ_src_t *src;
a_IRQ_src *src;
int i;
src = &opp->src[n_IRQ];
@ -399,8 +399,8 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
static void openpic_set_irq(void *opaque, int n_IRQ, int level)
{
openpic_t *opp = opaque;
IRQ_src_t *src;
a_openpic *opp = opaque;
a_IRQ_src *src;
src = &opp->src[n_IRQ];
DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
@ -420,7 +420,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
static void openpic_reset (void *opaque)
{
openpic_t *opp = (openpic_t *)opaque;
a_openpic *opp = (a_openpic *)opaque;
int i;
opp->glbc = 0x80000000;
@ -441,8 +441,8 @@ static void openpic_reset (void *opaque)
for (i = 0; i < MAX_CPU; i++) {
opp->dst[i].pctp = 0x0000000F;
opp->dst[i].pcsr = 0x00000000;
memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
memset(&opp->dst[i].raised, 0, sizeof(a_IRQ_queue));
memset(&opp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
}
/* Initialise timers */
for (i = 0; i < MAX_TMR; i++) {
@ -466,7 +466,7 @@ static void openpic_reset (void *opaque)
opp->glbc = 0x00000000;
}
static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
static inline uint32_t read_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg)
{
uint32_t retval;
@ -482,7 +482,7 @@ static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
return retval;
}
static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
static inline void write_IRQreg (a_openpic *opp, int n_IRQ,
uint32_t reg, uint32_t val)
{
uint32_t tmp;
@ -510,7 +510,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
#if 0 // Code provision for Intel model
#if MAX_DBL > 0
static uint32_t read_doorbell_register (openpic_t *opp,
static uint32_t read_doorbell_register (a_openpic *opp,
int n_dbl, uint32_t offset)
{
uint32_t retval;
@ -548,7 +548,7 @@ static void write_doorbell_register (penpic_t *opp, int n_dbl,
#endif
#if MAX_MBX > 0
static uint32_t read_mailbox_register (openpic_t *opp,
static uint32_t read_mailbox_register (a_openpic *opp,
int n_mbx, uint32_t offset)
{
uint32_t retval;
@ -568,7 +568,7 @@ static uint32_t read_mailbox_register (openpic_t *opp,
return retval;
}
static void write_mailbox_register (openpic_t *opp, int n_mbx,
static void write_mailbox_register (a_openpic *opp, int n_mbx,
uint32_t address, uint32_t value)
{
switch (offset) {
@ -586,10 +586,10 @@ static void write_mailbox_register (openpic_t *opp, int n_mbx,
#endif
#endif /* 0 : Code provision for Intel model */
static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
static void openpic_gbl_write (void *opaque, a_target_phys_addr addr, uint32_t val)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
a_openpic *opp = opaque;
a_IRQ_dst *dst;
int idx;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -646,9 +646,9 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
}
}
static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
static uint32_t openpic_gbl_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
uint32_t retval;
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@ -700,7 +700,7 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
int idx;
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@ -734,7 +734,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
uint32_t retval;
int idx;
@ -770,7 +770,7 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
int idx;
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@ -792,7 +792,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
static uint32_t openpic_src_read (void *opaque, uint32_t addr)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
uint32_t retval;
int idx;
@ -817,11 +817,11 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
return retval;
}
static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
static void openpic_cpu_write (void *opaque, a_target_phys_addr addr, uint32_t val)
{
openpic_t *opp = opaque;
IRQ_src_t *src;
IRQ_dst_t *dst;
a_openpic *opp = opaque;
a_IRQ_src *src;
a_IRQ_dst *dst;
int idx, s_IRQ, n_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -878,11 +878,11 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
}
}
static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
static uint32_t openpic_cpu_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *opp = opaque;
IRQ_src_t *src;
IRQ_dst_t *dst;
a_openpic *opp = opaque;
a_IRQ_src *src;
a_IRQ_dst *dst;
uint32_t retval;
int idx, n_IRQ;
@ -955,12 +955,12 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
}
static void openpic_buggy_write (void *opaque,
target_phys_addr_t addr, uint32_t val)
a_target_phys_addr addr, uint32_t val)
{
printf("Invalid OPENPIC write access !\n");
}
static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
static uint32_t openpic_buggy_read (void *opaque, a_target_phys_addr addr)
{
printf("Invalid OPENPIC read access !\n");
@ -968,9 +968,9 @@ static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
}
static void openpic_writel (void *opaque,
target_phys_addr_t addr, uint32_t val)
a_target_phys_addr addr, uint32_t val)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
addr &= 0x3FFFF;
DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
@ -989,9 +989,9 @@ static void openpic_writel (void *opaque,
}
}
static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
static uint32_t openpic_readl (void *opaque,a_target_phys_addr addr)
{
openpic_t *opp = opaque;
a_openpic *opp = opaque;
uint32_t retval;
addr &= 0x3FFFF;
@ -1028,10 +1028,10 @@ static CPUReadMemoryFunc * const openpic_read[] = {
static void openpic_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
openpic_t *opp;
a_openpic *opp;
DPRINTF("Map OpenPIC\n");
opp = (openpic_t *)pci_dev;
opp = (a_openpic *)pci_dev;
/* Global registers */
DPRINTF("Register OPENPIC gbl %08x => %08x\n",
addr + 0x1000, addr + 0x1000 + 0x100);
@ -1053,7 +1053,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
#endif
}
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
static void openpic_save_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
{
unsigned int i;
@ -1066,7 +1066,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
static void openpic_save(QEMUFile* f, void *opaque)
{
openpic_t *opp = (openpic_t *)opaque;
a_openpic *opp = (a_openpic *)opaque;
unsigned int i;
qemu_put_be32s(f, &opp->frep);
@ -1117,7 +1117,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
pci_device_save(&opp->pci_dev, f);
}
static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
static void openpic_load_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
{
unsigned int i;
@ -1130,7 +1130,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
openpic_t *opp = (openpic_t *)opaque;
a_openpic *opp = (a_openpic *)opaque;
unsigned int i;
if (version_id != 1)
@ -1184,7 +1184,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
return pci_device_load(&opp->pci_dev, f);
}
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
static void openpic_irq_raise(a_openpic *opp, int n_CPU, a_IRQ_src *src)
{
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
@ -1192,7 +1192,7 @@ static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *opp;
a_openpic *opp;
uint8_t *pci_conf;
int i, m;
@ -1200,7 +1200,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
if (nb_cpus != 1)
return NULL;
if (bus) {
opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
opp = (a_openpic *)pci_register_device(bus, "OpenPIC", sizeof(a_openpic),
-1, NULL, NULL);
if (opp == NULL)
return NULL;
@ -1215,7 +1215,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
pci_register_bar((PCIDevice *)opp, 0, 0x40000,
PCI_ADDRESS_SPACE_MEM, &openpic_map);
} else {
opp = qemu_mallocz(sizeof(openpic_t));
opp = qemu_mallocz(sizeof(a_openpic));
}
opp->mem_index = cpu_register_io_memory(openpic_read,
openpic_write, opp);
@ -1261,7 +1261,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
}
static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
static void mpic_irq_raise(a_openpic *mpp, int n_CPU, a_IRQ_src *src)
{
int n_ci = IDR_CI0 - n_CPU;
@ -1275,7 +1275,7 @@ static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
static void mpic_reset (void *opaque)
{
openpic_t *mpp = (openpic_t *)opaque;
a_openpic *mpp = (a_openpic *)opaque;
int i;
mpp->glbc = 0x80000000;
@ -1293,9 +1293,9 @@ static void mpic_reset (void *opaque)
for (i = 0; i < MAX_CPU; i++) {
mpp->dst[i].pctp = 0x0000000F;
mpp->dst[i].tfrr = 0x00000000;
memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
memset(&mpp->dst[i].raised, 0, sizeof(a_IRQ_queue));
mpp->dst[i].raised.next = -1;
memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
memset(&mpp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
mpp->dst[i].servicing.next = -1;
}
/* Initialise timers */
@ -1307,9 +1307,9 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x00000000;
}
static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
static void mpic_timer_write (void *opaque, a_target_phys_addr addr, uint32_t val)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
int idx, cpu;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -1340,9 +1340,9 @@ static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t va
}
}
static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
static uint32_t mpic_timer_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
uint32_t retval;
int idx, cpu;
@ -1375,10 +1375,10 @@ static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
return retval;
}
static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
static void mpic_src_ext_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
int idx = MPIC_EXT_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -1398,9 +1398,9 @@ static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
}
}
static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
static uint32_t mpic_src_ext_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
uint32_t retval;
int idx = MPIC_EXT_IRQ;
@ -1425,10 +1425,10 @@ static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
return retval;
}
static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
static void mpic_src_int_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
int idx = MPIC_INT_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -1448,9 +1448,9 @@ static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
}
}
static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
static uint32_t mpic_src_int_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
uint32_t retval;
int idx = MPIC_INT_IRQ;
@ -1475,10 +1475,10 @@ static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
return retval;
}
static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
static void mpic_src_msg_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
int idx = MPIC_MSG_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -1498,9 +1498,9 @@ static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
}
}
static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
static uint32_t mpic_src_msg_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
uint32_t retval;
int idx = MPIC_MSG_IRQ;
@ -1525,10 +1525,10 @@ static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
return retval;
}
static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
static void mpic_src_msi_write (void *opaque, a_target_phys_addr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
int idx = MPIC_MSI_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@ -1547,9 +1547,9 @@ static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
}
}
}
static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
static uint32_t mpic_src_msi_read (void *opaque, a_target_phys_addr addr)
{
openpic_t *mpp = opaque;
a_openpic *mpp = opaque;
uint32_t retval;
int idx = MPIC_MSI_IRQ;
@ -1657,16 +1657,16 @@ static CPUReadMemoryFunc * const mpic_msi_read[] = {
&mpic_src_msi_read,
};
qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *mpp;
a_openpic *mpp;
int i;
struct {
CPUReadMemoryFunc * const *read;
CPUWriteMemoryFunc * const *write;
target_phys_addr_t start_addr;
ram_addr_t size;
a_target_phys_addr start_addr;
a_ram_addr size;
} const list[] = {
{mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
{mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
@ -1681,7 +1681,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
if (nb_cpus != 1)
return NULL;
mpp = qemu_mallocz(sizeof(openpic_t));
mpp = qemu_mallocz(sizeof(a_openpic));
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;

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