motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-07 01:33:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc/pnv: Improve pervasive topology calculation for big-core

Browse source 
Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Caleb Schlossin 2024-02-27 14:36:23 -06:00 • committed by Nicholas Piggin
parent 0b8893236e
commit 9940412ae4
5 changed files with 57 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/ppc/pnv_chip.h
View file

@ -147,7 +147,7 @@ struct PnvChipClass {
DeviceRealize parent_realize;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);

1
include/hw/ppc/pnv_core.h
View file

@ -36,6 +36,7 @@ struct PnvCore {
/*< public >*/
PowerPCCPU **threads;
uint32_t pir;
uint32_t hwid;
uint64_t hrmor;
PnvChip *chip;