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target/mips: Add implementation of GINVT instruction

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Implement emulation of GINVT instruction. As QEMU doesn't support
caches and virtualization, this implementation covers only one
instruction (GINVT - Global Invalidate TLB) among all TLB-related
MIPS instructions.

Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Yongbok Kim 2019-12-20 10:29:34 +01:00 • committed by Aleksandar Markovic
parent feafe82cc2
commit 99029be1c2
7 changed files with 184 additions and 26 deletions
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2
target/mips/cpu.h
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@ -309,7 +309,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG04__USERLOCAL 2
#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
#define CP0_REG00__MMID 5
#define CP0_REG04__MMID 5
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1